#cva6 — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #cva6, aggregated by home.social.
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Oh falls ihr wegen der Arbyte oder wegen Toy Projekt weg von Asien und US Silizium kommen wollt, schaut Euch mal den #cva6 an: Ist ne 6-stage pipeline #riscv (32/64bit) Implementierung die #fpga und #asic ready und gut verifiziert ist. Basiert auf der Arbeit der ETH Zürich, wurde dann von Thales aus Frankreich weiter entwickelt und wird nun durch die OpenHW Group betreut - also nen echtes Europa Dings:
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#Virus associated with severe #HFMD found evolving with #risks of #outbreak: #China #CDC, https://www.globaltimes.cn/page/202405/1312928.shtml
#Coxsackievirus A6 (#CVA6), associated with severe hand, foot, and mouth disease (HFMD), is evolving and presents a risk of outbreak occurrence, according to research from the Chinese Center for Disease Control and Prevention (Chinese CDC). An immunologist told the Global Times on Thursday that vaccines would be an effective form of prevention.
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Boffins from ETH Zurich have devised a novel #fuzzer for finding bugs in #RISCV chips and have used it to find more than three dozen.
When applied to six actual RISC-V #CPU – #VexRiscv, #PicoRV32, #Kronos, #CVA6, Rocket, and BOOM – Cascade found 37 new bugs (translating to 29 #CVE) in five of these six designs. https://www.theregister.com/2023/10/24/cascade_fuzzer_zurich/ -
CW: research review
B. Sá et al., "CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration"¹
Virtualization is a key technology used in a wide range of applications, from cloud computing to embedded systems. Over the last few years, mainstream computer architectures were extended with hardware virtualization support, giving rise to a set of virtualization technologies (e.g., Intel VT, Arm VE) that are now proliferating in modern processors and SoCs. In this article, we describe our work on hardware virtualization support in the RISC-V CVA6 core. Our contribution is multifold and encompasses architecture, microarchitecture, and design space exploration. In particular, we highlight the design of a set of microarchitectural enhancements (i.e., G-Stage Translation Lookaside Buffer (GTLB), L2 TLB) to alleviate the virtualization performance overhead. We also perform a design space exploration (DSE) and accompanying post-layout simulations (based on 22nm FDX technology) to assess performance, power and area (PPA). Further, we map design variants on an FPGA platform (Genesys 2) to assess the functional performance-area trade-off. Based on the DSE, we select an optimal design point for the CVA6 with hardware virtualization support. For this optimal hardware configuration, we collected functional performance results by running the MiBench benchmark on Linux atop Bao hypervisor for a single-core configuration. We observed a performance speedup of up to 16\% (approx. 12.5\% on average) compared with virtualization-aware non-optimized design, at the minimal cost of 0.78\% in area and 0.33\% in power.
#arXiv #ResearchPapers #RISCV #Virtualisation #CVA6
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¹ https://arxiv.org/abs/2302.02969