home.social

#sve2 — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #sve2, aggregated by home.social.

  1. It would be very funny if a spec lawyering session on SVE2 accidentally uncovered a hypervisor bug in the worlds largest hypervisor vendor.

    #SVE #SVE2 #HPC #ARM

  2. It would be very funny if a spec lawyering session on SVE2 accidentally uncovered a hypervisor bug in the worlds largest hypervisor vendor.

    #SVE #SVE2 #HPC #ARM

  3. It would be very funny if a spec lawyering session on SVE2 accidentally uncovered a hypervisor bug in the worlds largest hypervisor vendor.

    #SVE #SVE2 #HPC #ARM

  4. It would be very funny if a spec lawyering session on SVE2 accidentally uncovered a hypervisor bug in the worlds largest hypervisor vendor.

    #SVE #SVE2 #HPC #ARM

  5. It would be very funny if a spec lawyering session on SVE2 accidentally uncovered a hypervisor bug in the worlds largest hypervisor vendor.

    #SVE #SVE2 #HPC #ARM

  6. What else?

    I do wonder if #MTE will be exposed this time around.

    Other questions? Do we *also* get real (read: full) #SVE and #SVE2
    if so, how wide per core?

    There's also the possibility of #sme2 but that's probably a step too far

  7. Resource:
    For those starting/looking at #SVE and #SVE2, @dougall made a superb instruction visualizer with presets for various Arm SVE enabled processors!

    Worth looking at to understanding what instructions are actually* doing under the hood: dougallj.github.io/asil/

    #HPC #arm #ASM

  8. Google pixel is getting #ARMV9 LETS GOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOOO

    Full #SVE 1 and #SVE2!

    #pixel

  9. ARM (aarch_64):
    #SVE2 Using a phone as a dev board, you're good to go. Latest flagship Samsung, OnePlus phones feature SVE2.
    #SME Not accessible yet. Maybe we'll see dev boards, but for now it's [redacted] only.

    RISC-V:
    #RISCVV: Prelaunch spec Dev boards exist, but not much exists with the 1.0 (or higher) spec implemented in hardware.
    #RISCVM: FPGA prototyping only, spec is WIP

    Use an FPGA ¯\_(ツ)_/¯