#pldev — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #pldev, aggregated by home.social.
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I built an esoteric programming language: https://rphle.de/tzap/
It only has 4 instructions and no arbitrary values like numbers or memory addresses.
I challenge you to implement Fibonacci in it!#esolang #pldev #programming #programminglanguages #challenge
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I built an esoteric programming language: https://rphle.de/tzap/
It only has 4 instructions and no arbitrary values like numbers or memory addresses.
I challenge you to implement Fibonacci in it!#esolang #pldev #programming #programminglanguages #challenge
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I built an esoteric programming language: https://rphle.de/tzap/
It only has 4 instructions and no arbitrary values like numbers or memory addresses.
I challenge you to implement Fibonacci in it!#esolang #pldev #programming #programminglanguages #challenge
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I built an esoteric programming language: https://rphle.de/tzap/
It only has 4 instructions and no arbitrary values like numbers or memory addresses.
I challenge you to implement Fibonacci in it!#esolang #pldev #programming #programminglanguages #challenge
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I built an esoteric programming language: https://rphle.de/tzap/
It only has 4 instructions and no arbitrary values like numbers or memory addresses.
I challenge you to implement Fibonacci in it!#esolang #pldev #programming #programminglanguages #challenge
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The latest iteration of number_loops() which is giving me encouraging results, at least on the test case scribbled above...
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The latest iteration of number_loops() which is giving me encouraging results, at least on the test case scribbled above...
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The latest iteration of number_loops() which is giving me encouraging results, at least on the test case scribbled above...
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The latest iteration of number_loops() which is giving me encouraging results, at least on the test case scribbled above...
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The latest iteration of number_loops() which is giving me encouraging results, at least on the test case scribbled above...
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A visual aid while debugging code to identify backward branches, number loops, etc...
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A visual aid while debugging code to identify backward branches, number loops, etc...
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A visual aid while debugging code to identify backward branches, number loops, etc...
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A visual aid while debugging code to identify backward branches, number loops, etc...
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A visual aid while debugging code to identify backward branches, number loops, etc...
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The graphs generated by iongraph (a Mozilla tool for SpiderMonkey) are a lot nicer than just trying to wrangle reasonable outputs from graphviz:
https://github.com/mozilla-spidermonkey/iongraphNice writeup about the layout algorithm here:
https://spidermonkey.dev/blog/2025/10/28/iongraph-web.htmlStrong temptation to build some custom graph generation tooling for my own language hackery. Looking at lightweight PDF generation libraries.
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The graphs generated by iongraph (a Mozilla tool for SpiderMonkey) are a lot nicer than just trying to wrangle reasonable outputs from graphviz:
https://github.com/mozilla-spidermonkey/iongraphNice writeup about the layout algorithm here:
https://spidermonkey.dev/blog/2025/10/28/iongraph-web.htmlStrong temptation to build some custom graph generation tooling for my own language hackery. Looking at lightweight PDF generation libraries.
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The graphs generated by iongraph (a Mozilla tool for SpiderMonkey) are a lot nicer than just trying to wrangle reasonable outputs from graphviz:
https://github.com/mozilla-spidermonkey/iongraphNice writeup about the layout algorithm here:
https://spidermonkey.dev/blog/2025/10/28/iongraph-web.htmlStrong temptation to build some custom graph generation tooling for my own language hackery. Looking at lightweight PDF generation libraries.
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The graphs generated by iongraph (a Mozilla tool for SpiderMonkey) are a lot nicer than just trying to wrangle reasonable outputs from graphviz:
https://github.com/mozilla-spidermonkey/iongraphNice writeup about the layout algorithm here:
https://spidermonkey.dev/blog/2025/10/28/iongraph-web.htmlStrong temptation to build some custom graph generation tooling for my own language hackery. Looking at lightweight PDF generation libraries.
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The graphs generated by iongraph (a Mozilla tool for SpiderMonkey) are a lot nicer than just trying to wrangle reasonable outputs from graphviz:
https://github.com/mozilla-spidermonkey/iongraphNice writeup about the layout algorithm here:
https://spidermonkey.dev/blog/2025/10/28/iongraph-web.htmlStrong temptation to build some custom graph generation tooling for my own language hackery. Looking at lightweight PDF generation libraries.
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Anyone know of any good writeups out there on the reverse linear scan register allocation (on SSA form IR).
I'm especially interested in discussion of register usage hints or constraints around things like calling conventions -- landing parameters in the right registers, but making the most of those registers outside of call boundaries, etc.
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Anyone know of any good writeups out there on the reverse linear scan register allocation (on SSA form IR).
I'm especially interested in discussion of register usage hints or constraints around things like calling conventions -- landing parameters in the right registers, but making the most of those registers outside of call boundaries, etc.
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Anyone know of any good writeups out there on the reverse linear scan register allocation (on SSA form IR).
I'm especially interested in discussion of register usage hints or constraints around things like calling conventions -- landing parameters in the right registers, but making the most of those registers outside of call boundaries, etc.
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Anyone know of any good writeups out there on the reverse linear scan register allocation (on SSA form IR).
I'm especially interested in discussion of register usage hints or constraints around things like calling conventions -- landing parameters in the right registers, but making the most of those registers outside of call boundaries, etc.
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Anyone know of any good writeups out there on the reverse linear scan register allocation (on SSA form IR).
I'm especially interested in discussion of register usage hints or constraints around things like calling conventions -- landing parameters in the right registers, but making the most of those registers outside of call boundaries, etc.
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Implemented the RV32I pass-by-register calling convention in the simple SR32 code generator... as a compiler parameter.
Updated the emulator to support either calling convention (at runtime) for syscalls.
This all works, which is nice, but now I've just added a third dimension to the test grid, which is less nice.
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Implemented the RV32I pass-by-register calling convention in the simple SR32 code generator... as a compiler parameter.
Updated the emulator to support either calling convention (at runtime) for syscalls.
This all works, which is nice, but now I've just added a third dimension to the test grid, which is less nice.
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Implemented the RV32I pass-by-register calling convention in the simple SR32 code generator... as a compiler parameter.
Updated the emulator to support either calling convention (at runtime) for syscalls.
This all works, which is nice, but now I've just added a third dimension to the test grid, which is less nice.
-
Implemented the RV32I pass-by-register calling convention in the simple SR32 code generator... as a compiler parameter.
Updated the emulator to support either calling convention (at runtime) for syscalls.
This all works, which is nice, but now I've just added a third dimension to the test grid, which is less nice.
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Implemented the RV32I pass-by-register calling convention in the simple SR32 code generator... as a compiler parameter.
Updated the emulator to support either calling convention (at runtime) for syscalls.
This all works, which is nice, but now I've just added a third dimension to the test grid, which is less nice.
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The desire to explore Subnautica 2 (now in early access) is warring with the desire to generate assembly from IR now that register allocation is happening.
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The desire to explore Subnautica 2 (now in early access) is warring with the desire to generate assembly from IR now that register allocation is happening.
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The desire to explore Subnautica 2 (now in early access) is warring with the desire to generate assembly from IR now that register allocation is happening.
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The desire to explore Subnautica 2 (now in early access) is warring with the desire to generate assembly from IR now that register allocation is happening.
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The desire to explore Subnautica 2 (now in early access) is warring with the desire to generate assembly from IR now that register allocation is happening.
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Rearranged the register assignments in my softrisc32 ISA to match that of RV32I because there's no point in maintaining a variant register map just because I find the RV32I map "untidy" (due to them arranging stuff to make sense when the top half are missing in RV32E).
This has the side-effect of making (textual) sr32 assembly even closer to rv32i assembly.
About to shift from passing parameters on the stack to passing parameters in registers.
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Rearranged the register assignments in my softrisc32 ISA to match that of RV32I because there's no point in maintaining a variant register map just because I find the RV32I map "untidy" (due to them arranging stuff to make sense when the top half are missing in RV32E).
This has the side-effect of making (textual) sr32 assembly even closer to rv32i assembly.
About to shift from passing parameters on the stack to passing parameters in registers.
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Rearranged the register assignments in my softrisc32 ISA to match that of RV32I because there's no point in maintaining a variant register map just because I find the RV32I map "untidy" (due to them arranging stuff to make sense when the top half are missing in RV32E).
This has the side-effect of making (textual) sr32 assembly even closer to rv32i assembly.
About to shift from passing parameters on the stack to passing parameters in registers.
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Rearranged the register assignments in my softrisc32 ISA to match that of RV32I because there's no point in maintaining a variant register map just because I find the RV32I map "untidy" (due to them arranging stuff to make sense when the top half are missing in RV32E).
This has the side-effect of making (textual) sr32 assembly even closer to rv32i assembly.
About to shift from passing parameters on the stack to passing parameters in registers.
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Rearranged the register assignments in my softrisc32 ISA to match that of RV32I because there's no point in maintaining a variant register map just because I find the RV32I map "untidy" (due to them arranging stuff to make sense when the top half are missing in RV32E).
This has the side-effect of making (textual) sr32 assembly even closer to rv32i assembly.
About to shift from passing parameters on the stack to passing parameters in registers.
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Starting to allocate some registers. I need more test cases with greater register pressure. Most of them fit within 4 working registers just fine.
I did update my live range graph in the IR dump to use dashed lines for spilled registers.
Here's one that spills at 4 and spills a bit more at 3.
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Starting to allocate some registers. I need more test cases with greater register pressure. Most of them fit within 4 working registers just fine.
I did update my live range graph in the IR dump to use dashed lines for spilled registers.
Here's one that spills at 4 and spills a bit more at 3.
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Starting to allocate some registers. I need more test cases with greater register pressure. Most of them fit within 4 working registers just fine.
I did update my live range graph in the IR dump to use dashed lines for spilled registers.
Here's one that spills at 4 and spills a bit more at 3.
-
Starting to allocate some registers. I need more test cases with greater register pressure. Most of them fit within 4 working registers just fine.
I did update my live range graph in the IR dump to use dashed lines for spilled registers.
Here's one that spills at 4 and spills a bit more at 3.
-
Starting to allocate some registers. I need more test cases with greater register pressure. Most of them fit within 4 working registers just fine.
I did update my live range graph in the IR dump to use dashed lines for spilled registers.
Here's one that spills at 4 and spills a bit more at 3.
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Housekeeping to allow the -out path (for final compilation) and the -xir path (for eXecutable IR useful for validation) to coexist in a single compiler invocation. Also some tidying up of argument wrangling, improving the XIR format so writing it is non-destructive (to allow generating pre/post optimization variants), tidying up output file argument handling in main, and separate flags for dumping ir0 (initial IR generated from the AST) and -ir1 (final IR).
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Housekeeping to allow the -out path (for final compilation) and the -xir path (for eXecutable IR useful for validation) to coexist in a single compiler invocation. Also some tidying up of argument wrangling, improving the XIR format so writing it is non-destructive (to allow generating pre/post optimization variants), tidying up output file argument handling in main, and separate flags for dumping ir0 (initial IR generated from the AST) and -ir1 (final IR).
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Housekeeping to allow the -out path (for final compilation) and the -xir path (for eXecutable IR useful for validation) to coexist in a single compiler invocation. Also some tidying up of argument wrangling, improving the XIR format so writing it is non-destructive (to allow generating pre/post optimization variants), tidying up output file argument handling in main, and separate flags for dumping ir0 (initial IR generated from the AST) and -ir1 (final IR).
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Housekeeping to allow the -out path (for final compilation) and the -xir path (for eXecutable IR useful for validation) to coexist in a single compiler invocation. Also some tidying up of argument wrangling, improving the XIR format so writing it is non-destructive (to allow generating pre/post optimization variants), tidying up output file argument handling in main, and separate flags for dumping ir0 (initial IR generated from the AST) and -ir1 (final IR).
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Housekeeping to allow the -out path (for final compilation) and the -xir path (for eXecutable IR useful for validation) to coexist in a single compiler invocation. Also some tidying up of argument wrangling, improving the XIR format so writing it is non-destructive (to allow generating pre/post optimization variants), tidying up output file argument handling in main, and separate flags for dumping ir0 (initial IR generated from the AST) and -ir1 (final IR).