#instructionsetarchitecture — Public Fediverse posts

RISC-V Europe Summit 2026: Beyond Embedded Electronics

//php echo do_shortcode(‘[responsivevoice_button voice=”US English Male” buttontext=”Listen to Post”]’) ?> The RISC-V Summit Europe 2026, held last month…
#Europe #EU #datacenters #edgeAI #InstructionSetArchitecture #PhysicalAI #RISC-V #RISC-VEuropeSummit #spaceapplications
https://www.europesays.com/europe/97934/

A SHA instruction set is a set of extensions to the #ARM, #RISCV and #x86 #instructionSetArchitecture which support #hardwareAcceleration of the #SecureHashAlgorithm (SHA) family.

A SHA instruction set is a set of extensions to the #ARM, #RISCV and #x86 #instructionSetArchitecture which support #hardwareAcceleration of the #SecureHashAlgorithm (SHA) family.

Checking In On the ISA Wars and Its Impact on CPU Architectures https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #Microcontrollers #CurrentEvents #hardware #Interest #CPUISA #RISC-V #x86_64 #mips #ARM

Checking In On the ISA Wars and Its Impact on CPU Architectures https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #Microcontrollers #CurrentEvents #hardware #Interest #CPUISA #RISC-V #x86_64 #mips #ARM

Checking In On the ISA Wars and Its Impact on CPU Architectures https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #Microcontrollers #CurrentEvents #hardware #Interest #CPUISA #RISC-V #x86_64 #mips #ARM

Checking In On the ISA Wars and Its Impact on CPU Architectures https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #Microcontrollers #CurrentEvents #hardware #Interest #CPUISA #RISC-V #x86_64 #mips #ARM

Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #microcontrollers #currentevents #hardware #interest #cpuisa #risc-v #x86_64 #mips #arm

Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #microcontrollers #currentevents #hardware #interest #cpuisa #risc-v #x86_64 #mips #arm

Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #microcontrollers #currentevents #hardware #interest #cpuisa #risc-v #x86_64 #mips #arm

Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #microcontrollers #currentevents #hardware #interest #cpuisa #risc-v #x86_64 #mips #arm

Checking In On the ISA Wars and Its Impact on CPU Architectures - An Instruction Set Architecture (ISA) defines the software interface through which... - https://hackaday.com/2025/03/18/checking-in-on-the-isa-wars-and-its-impact-on-cpu-architectures/ #instructionsetarchitecture #microcontrollers #currentevents #hardware #interest #cpuisa #risc-v #x86_64 #mips #arm

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V Vector Extension overview
🔗 http://0x80.pl/notesen/2024-11-09-riscv-vector-extension.html

"The goal of this text is to provide an overview of RISC-V Vector extension (RVV), and compare — when applicable — with widespread SIMD vector instruction sets: SSE, AVX, AVX-512, ARM Neon and SVE.
[…]
The vector extension is quite a huge addition. It adds 302 instructions plus four highly configurable load & store operations."

#RISCV #RISC_V #RVV #ComputerArchitecture #ISA #InstructionSetArchitecture #CPU #CPUs #processor #processors

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

RISC-V State of the Union — current highlights and roadmap of RISC-V by RISC-V's chief architect
🎞 https://yewtu.be/watch?v=_oLVPFQvJbI
Slides: https://riscv-europe.org/summit/2024/media/proceedings/plenary/Tue-11-30-Krste-Asanovic.pdf

#RISCV #RISC #CPU #CPUs #architecture #ComputerArchitecture #processor #processors #ISA #InstructionSetArchitecture #hardware

If it's $1 Trillion or if it's $7 Trillion, would it go towards Open #RISC #RISCV #OpenISA #ISA #InstructionSetArchitecture #OpenInstructionSetArchitecture ?

https://www.tomshardware.com/tech-industry/artificial-intelligence/jim-keller-responds-to-sam-altmans-plan-to-raise-dollar7-billion-to-make-ai-chips

The development of the RISC-V open standard Instruction Set Architecture https://thechipletter.substack.com/p/risc-v-part-1-origins-and-architecture #RISC-V #processors #cpu #instructionsetarchitecture

The development of the RISC-V open standard Instruction Set Architecture https://thechipletter.substack.com/p/risc-v-part-1-origins-and-architecture #RISC-V #processors #cpu #instructionsetarchitecture

Software Defined… CPU? - Everything is better when you can program it, right? We have software-defined radi... - https://hackaday.com/2021/07/19/software-defined-cpu/ #instructionsetarchitecture #instructionset #computerhacks #news #cpu #isa #x86

RISC-V: Why The ISA Battles Aren’t Over Yet - A computer processor uses a so-called Instruction Set Architecture to talk with the world outside of... more: https://hackaday.com/2019/11/12/risc-v-why-the-isa-battles-arent-over-yet/ #instructionsetarchitecture #microcontrollers #engineering #featured #ibmpower #openrisc #risc-v #power #sparc #mips #arm #isa