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152 results for “hansfbaier”
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GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP receiver also seems to be working with internal loopback with the #openXC7 #opensource #FPGA toolchain. LED patterns shows receiver data (a counter), and it is qualitatively the same as the vivado version.
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GTP Transceivers are now also working with internal refclk on Xilinx Artix FPGAs with the #openXC7 #opensource #FPGA #toolchain
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Ported Minimig-AGA to the Xilinx-#MiSTeX #FPGA #retrogaming platform today.
Basically works (Kickstart 1.3 boots), but has lots of bugs (graphical glitches, floppy hangs on load). -
First signs of life from the GTP Multi-Gigabit Transceivers using the #openXC7 #opensource #FPGA toolchain on an Artix7 FPGA. This was several months of work.
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Building 11 @topapate #retrogaming #MiSTeX cores simultaneously on an AWS 32 core 128GB RAM machine, for Kintex 325T.
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There is now a binary repository with ready made bitstreams for the #MiSTeX #retrogaming #FPGA project.
https://github.com/MiSTeX-devel/MiSTeX-bin -
Three more #retrogaming #arcade #FPGA cores from @topapate working on #MiSTeX on Xilinx!
We now have a total of 47 working JOTEGO cores!
https://github.com/MiSTeX-devel/MiSTeX-ports/tree/main/cores -
The Bubble Bobble arcade core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 10 minutes. -
The 1943 core is now working on #Xilinx #FPGA s on the #MiSTeX #retrogaming platform.
Thanks to the great work of @somhi (on GitHub) , this port only took 30 minutes. -
The 1942 core is now working on #Xilinx #FPGAs on the #MiSTeX #retrogaming platform.
Thanks to the fantastic work of @somhi (on GitHub),
I could write a shell script which automates most of the gruntwork of the porting process.
This is the first one ported with that script.
I did the script and this port in a couple of hours. -
The first core using the JOTEGO's (@topapate) framework is working on Xilinx FPGAs on the #MiSTeX #retrogaming #FPGA platform!
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First blinky greetings from the GTPE2_COMMON PLL using the #openXC7 #opensource #FPGA toolchain.
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Nice!
The #openxc7 #opensource #FPGA toolchain already seems to be able to place GTP transceivers.
I only still have to figure out how to use an internal refclk, something even Vivado only does under protest (DRC rule downgrade). -
The #MiSTeX #fpga #retrogaming baseboard rev2 has arrived!
It has the MiSTeX logo and an additional trace from the
HPS to the RP2040, to allow updating the RP2040 firmware from the HPS linux system. And latching switches. -
Thanks @lu_source
for covering the #MiSTeX #retrogaming #FPGA project -
NES now works on the #MiSTeX #FPGA #retrogaming console! (With limitations, no savestates, no PAL/NTSC)
Also: Now the full 256 MB of DDR3 memory are useable on the QMTech Xilinx boards (previously 128MB) and the bandwidth is double too (16 bit access instead of 8 bit) -
Thanks Chandler Klüser for covering the #MiSTeX project
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That is how revision 2 of the #MiSTeX #FPGA #retrogaming baseboard looks like now.
Details on my patreon:
https://t.co/y7JZfGUDnU -
rev2 of the #MiSTeX #retrogaming #FPGA baseboard is upcoming, fixing the (minor) issues of rev1, moving to KiCAD8 and using @baxysquare ' s cute MiSTeX-Kun mascot.
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The rev1 #MiSTeX #opensource #retrogaming baseboard has arrived from @JLCPCB and it's beautiful!
Already tested, SNAC works now, HDMI works, VGA works, JTAG (rp2040) works, audio works. Looking good! The side switches I got wrong (momentary vs latched), but that is fixed now. -
I sent revision 1 of the #MiSTeX #FPGA #retrogaming #console to the fab @JLCPCB yesterday!
Many improvements: External button/power switch connectors, signal integrity, ESD protection, test points, better headphone connector. USB docking points.
RP2040 LED and analog ins. -
This week's work. Implement dynamic reconfiguration core for #Xilinx #FPGAs. Integrate into #MiSTeX #opensource #retrogames #console. Now changing video modes and #HDMI works with Xilinx FPGAs for the first time. Up to 1366x768@60. FullHD not yet. Hope for the new board revision.
VGA works with 1080p. -
Just got a dynamic reconfiguration core working for the MMCME2_ADV using the #openXC7 #opensource #FPGA toolchain. Should also work with minor modifications for the PLLE2_ADV (upcoming).
This took 10 seconds to compile and 5 seconds to upload to the FPGA, using 100% open source tools. Compare that with Vivado!
My first nontrivial piece of #Verilog !
Here is the source:
https://github.com/openXC7/primitive-tests/blob/main/mmcm-reconfig/xilinx7_reconfig.v