#uvvm — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #uvvm, aggregated by home.social.
-
Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.
Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!
I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!