#uvvm — Public Fediverse posts

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

Well after 14 years I'm laid off from Viavi. This has been a particular nightmare for me for 14 years since I was a victim of the 2008 financial meltdown and laid off then and couldn't find work for all of 2009. It was rough.

But anyway, locally fantastic staff and great people to work with. Higher management, no comment as I am negatively biased. We made some cool stuff and I will miss seeing how my current baby will turn out.

Anyhow I don't really know how far this might go, but if someone is looking for a #EE with 25 years experience in digital design primarily with #FPGA and #VHDL (and a smattering of #Verilog), including verification mainly using #OSVVM and #UVVM (the latter modeled after #UVM) please contact me, especially if you can support remote work. I do have a professional office at home, it can be YOURS (along with me of course).

(And if so inclined, boosting this for greater visibility in networks is greatly appreciated.)

Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.

Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!

I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!

#vhdl #verilog #fpga #uvvm #aldec #avalon

Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.

Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!

I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!

#vhdl #verilog #fpga #uvvm #aldec #avalon

Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.

Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!

I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!

#vhdl #verilog #fpga #uvvm #aldec #avalon

Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.

Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!

I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!

#vhdl #verilog #fpga #uvvm #aldec #avalon

Always interesting to learn a new tool. We'd picked up on UVVM (Universal VHDL Verification Methodology) library from some Aldec online seminars and were impressed with their breadth of library functions. I took it upon myself to use a block I've used a few places, an asynchronous FIFO, thinking it would be a great object to test as it was working well. I had designed it to have an Avalon Streaming style interface for in and out.

Well I got it verified but along the way discovered that the Avalon Streaming self-imposed requirement wasn't verifiable, and it involved going down a rabbithole on simulation/synthesis behavior mismatch, inferring block RAM with first word fall through in VHDL and Verilog, and more. Definitely an eye-opening effort!

I have it spiffed up quite nicely, now just have to check places where it was used -- those places I probably designed around my own flaws. Good library!!

#vhdl #verilog #fpga #uvvm #aldec #avalon