home.social

#siemenseda — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #siemenseda, aggregated by home.social.

  1. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  2. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  3. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  4. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  5. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  6. Für die Entwicklung von Halbleitern kommen essenzielle Tools vorwiegend aus den USA. Chinesische Hersteller wollen für mögliche Handelskriege vorbereitet sein.
    Angst vor Sanktionen: Chinesische Chiphersteller wollen weg von US-Software