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#siemenseda — Public Fediverse posts

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  1. Siemens Automates Chip Design with AI Agents: “Verification and Fixes While Engineers Sleep” — BigGo Finance

    Global electronic design automation (EDA) company Siemens EDA is aggressively pursuing an “AI-Native Design” strategy that embeds artificial…
    #Germany #DE #Europe #EU #Europa #Siemens #AnchorGupta #Anthropic #Cadence #Calibre #Fuse #Google #Nemotron #Nvidia #OpenAI #Questa #siemens #SiemensEDA #Synopsys #Tessent
    europesays.com/germany/70312/

  2. Siemens Hooks Chip Design Agents to Physics Engines to Prevent Tapeout Errors

    Chip design teams have lived with a specific nightmare for as long as AI has been promising to…
    #Germany #DE #Europe #EU #Europa #Siemens #AI #chipdesign #chipdesignverificationAI #EDAagenticAI #Nvidia #semiconductor #siemens #SiemensEDA
    europesays.com/germany/62153/

  3. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  4. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  5. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  6. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  7. 🗓️ Verification Academy Live BRNO
    May 21 2026 in Brno, Czech Republic

    Three main topics on the table:
    - Questa One & faster verification closure
    - Static/formal verification
    - AI in verification workflows

    In-person only. Brno University of Technology, Bozetechova, Room A112.

    verificationacademy.com/topics

    #QuestaOne #SystemVerilog #UVM #FPGA #ASIC #FormalVerification #SiemensEDA

  8. Für die Entwicklung von Halbleitern kommen essenzielle Tools vorwiegend aus den USA. Chinesische Hersteller wollen für mögliche Handelskriege vorbereitet sein.
    Angst vor Sanktionen: Chinesische Chiphersteller wollen weg von US-Software
  9. Für die Entwicklung von Halbleitern kommen essenzielle Tools vorwiegend aus den USA. Chinesische Hersteller wollen für mögliche Handelskriege vorbereitet sein.
    Angst vor Sanktionen: Chinesische Chiphersteller wollen weg von US-Software