#rustsbi — Public Fediverse posts

Gotta ramp things up a bit, so here's news on #oreboot on the #VisionFive: I've figured out that we already had the code for switching to the other UART pin header, and documented and reenabled things.

So yay, we can now start booting from SRAM and output is good! \o/

In next week's live stream, we'll see about a second stage where we bring #RustSBI into the mix. We may introduce the #xtask based build setup already.

Here is how #oreboot is pieced together:
We start from a ROM with SRAM, initialize the platform, set up DRAM, copy the next stage into it, and continue there. On RISC-V, we pull in #RustSBI for the SBI implementation. Then we execute #LinuxBoot or any other payload.

With u-root in #LinuxBoot, we offer a common #Linux environment including all the usual commands such as cat, ls, etc, plus boot loaders that can boot into the final OS - e.g., another Linux system. 🐧

IT WORKS!!!!! 🥳

We can now fully boot the Allwinner D1 RISC-V SoC in #Rust, from flash right into #Linux, demoed on a Lichee RV + Dock. :-)

The full flow:
boot0 (ROM/SRAM) -> #oreboot (DRAM) + #RustSBI -> #LinuxBoot (Linux + u-root)

The last issue was a stupid one again. I had sorta crapped up arithmetics again. :D

If you have a D1 with a NOR flash (16MB / 128Mbit), you can try it out:
https://metaspora.org/oreboot-linuxboot-licheerv-spinor.rom

In the coming weeks, we will iron a few things out and do a writeup on everything.

What's up? We have graphics output on the Sipeed Lichee RV module with a little test program written in Go as part of u-root, plus the #Linux #framebuffer console.
✨👩‍💻✨
This is #oreboot + @LinuxBootOrg on #RISCV. :-)
The SBI implementation is Luo Jia's #RustSBI. It allows us to keep everything before Linux fully in #Rust. \o/

If you have one such module, let me know and I can provide you with an image and how to load and run it. :-)

More to follow when carrier boards arrive in a few weeks.