home.social

Search

1000 results for “madrox”

  1. Off to #Retrofest about 11, should be there around midday, looking forward to a few nerdy hours and meeting some people I know from here :)
    @DosFox @rc2014

  2. So what would you do?
    1) waste £12k and 4 years of spare time?
    2) spend another year of spare time and ~£4K getting the improved version done?

    Here’s a video of where I was at middle of last year (most of the time spent since has been trying to find raise and get feedback).

    Delta Demo and run through video
    youtu.be/jpkybukyXss

    Thoughts?

    #synth #synthesizer #WhatToDo #diy

    4/4

  3. I have toooo many knickknacks, but I can't help myself! 😄🤷🏼‍♀️ #stuff #crystals #rocks #blueglass

  4. IT WORKS!!!

    With a bit of effort I can now receive data from the UART on my keyboard controller, into the CPLD and read it form BASIC on my 6502 laptop revision b (slim version).

    I've set the Keyboard controller to output characters from $20 to $7F, here you can see them being shown.

    There is also a "new data received" status register too!

    #CPLD #LT6502B

  5. IT WORKS!!!

    With a bit of effort I can now receive data from the UART on my keyboard controller, into the CPLD and read it form BASIC on my 6502 laptop revision b (slim version).

    I've set the Keyboard controller to output characters from $20 to $7F, here you can see them being shown.

    There is also a "new data received" status register too!

    #CPLD #LT6502B

  6. IT WORKS!!!

    With a bit of effort I can now receive data from the UART on my keyboard controller, into the CPLD and read it form BASIC on my 6502 laptop revision b (slim version).

    I've set the Keyboard controller to output characters from $20 to $7F, here you can see them being shown.

    There is also a "new data received" status register too!

    #CPLD #LT6502B

  7. IT WORKS!!!

    With a bit of effort I can now receive data from the UART on my keyboard controller, into the CPLD and read it form BASIC on my 6502 laptop revision b (slim version).

    I've set the Keyboard controller to output characters from $20 to $7F, here you can see them being shown.

    There is also a "new data received" status register too!

    #CPLD #LT6502B

  8. Well the CPLD UART is coming along, another big step... Now when it's done receiving a byte, it transfers it to a register, which can then be read at anytime by the CPU. So that the CPU doesn't read garbage if it tries to read mid transfer (double buffer).

    more to do yet as I need two such registers and I also want the register to be cleared once it's been read, but this is BIG progress.

    This is all done in WINCUPL, not VHDL/Verilog.

    #CPLD #LT6502b

  9. Well the CPLD UART is coming along, another big step... Now when it's done receiving a byte, it transfers it to a register, which can then be read at anytime by the CPU. So that the CPU doesn't read garbage if it tries to read mid transfer (double buffer).

    more to do yet as I need two such registers and I also want the register to be cleared once it's been read, but this is BIG progress.

    This is all done in WINCUPL, not VHDL/Verilog.

    #CPLD #LT6502b

  10. Well the CPLD UART is coming along, another big step... Now when it's done receiving a byte, it transfers it to a register, which can then be read at anytime by the CPU. So that the CPU doesn't read garbage if it tries to read mid transfer (double buffer).

    more to do yet as I need two such registers and I also want the register to be cleared once it's been read, but this is BIG progress.

    This is all done in WINCUPL, not VHDL/Verilog.

    #CPLD #LT6502b

  11. Well the CPLD UART is coming along, another big step... Now when it's done receiving a byte, it transfers it to a register, which can then be read at anytime by the CPU. So that the CPU doesn't read garbage if it tries to read mid transfer (double buffer).

    more to do yet as I need two such registers and I also want the register to be cleared once it's been read, but this is BIG progress.

    This is all done in WINCUPL, not VHDL/Verilog.

    #CPLD #LT6502b

  12. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  13. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  14. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  15. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  16. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  17. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  18. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  19. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  20. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  21. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  22. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD