#sv32 — Public Fediverse posts
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For an RV32IMA core design, I'm considering implementing the Sv32 MMU using a software-managed TLB, as was commonly done on MIPS and Alpha, instead of hardware table walk. This would use custom CSRs.
Are there any existing RISC-V implementations that use software-managed TLB? The RISC-V Privileged spec leaves open the possibility.
#riscv #sv32 #mmu #tlb