#timingclosure — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #timingclosure, aggregated by home.social.
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Clock gates in an FPGA design are the evil spawn of anitchrist. An ASIC-based design I am trying to stuff into an FPGA has some clock gates that are for power handling (ignorable) while others are for datapath operations (not-ignorable).
The datapath clock gate concept is new to me as normal FPGA design will gate the D inputs with a combinatorial cloud. This ASIC RTL will just shut the clock off to disable the dataflow.