#picogarry — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #picogarry, aggregated by home.social.
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Part four of the Pico Garry project: Driving the /ROMEN and /RAMRD signals. These are triggered during an MREQ and depend on the states of /RD, A15 and A14 as well as the upper and lower ROM enable states.
This is far more than an RP PIO can handle unless you use cleverly tricks. In this case I use a jump table and use the input pin values to set the program counter. ROM enable changes will modify the jump table program code.
https://bread80.com/2024/11/11/pico-garry-2350-part-4-memory-read-select/
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Part four of the Pico Garry project: Driving the /ROMEN and /RAMRD signals. These are triggered during an MREQ and depend on the states of /RD, A15 and A14 as well as the upper and lower ROM enable states.
This is far more than an RP PIO can handle unless you use cleverly tricks. In this case I use a jump table and use the input pin values to set the program counter. ROM enable changes will modify the jump table program code.
https://bread80.com/2024/11/11/pico-garry-2350-part-4-memory-read-select/
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Have you ever seen a jump table implemented on an RP2xxx PIO? If not his is a fun one.
The ROMEN and RAMRD signals enable either ROM or RAM when an /MREQ happens. I'm reusing code from the previous Pico Garry. It's triggered by /MREQ, reads A15, A14, /RD and loads the value into the program counter (ie. it jumps to the address read from the pins).
When ROM enable states change instructions will be 'poked' into the PIOs address space by main core.
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Have you ever seen a jump table implemented on an RP2xxx PIO? If not his is a fun one.
The ROMEN and RAMRD signals enable either ROM or RAM when an /MREQ happens. I'm reusing code from the previous Pico Garry. It's triggered by /MREQ, reads A15, A14, /RD and loads the value into the program counter (ie. it jumps to the address read from the pins).
When ROM enable states change instructions will be 'poked' into the PIOs address space by main core.
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Pico Garry 2350 Part 3: The 'conditional signals' (/244EN, /MWE and /CAS) which are asserted for a portion of the gate array cycle only if an input pin is asserted (or de-asserted). https://bread80.com/2024/09/16/pico-garry-2350-part-3-csigs-conditional-signals/
#PicoGarry #PicoGarry2350 #Amstrad #AmstradCPC #GateArray #RP2350
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Pico Garry 2350 Part 3: The 'conditional signals' (/244EN, /MWE and /CAS) which are asserted for a portion of the gate array cycle only if an input pin is asserted (or de-asserted). https://bread80.com/2024/09/16/pico-garry-2350-part-3-csigs-conditional-signals/
#PicoGarry #PicoGarry2350 #Amstrad #AmstradCPC #GateArray #RP2350
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Time for an afternoon of Pico Garry - which started with me discovering a few pinout issues. This is the schematic for an temporary adapter board to use a PGA2350 which I was printing to use as a reference while I probed a few pins. But the pinout on the 'South' side was wrong.
Thankfully discovered before I sent to the fab...
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Time for an afternoon of Pico Garry - which started with me discovering a few pinout issues. This is the schematic for an temporary adapter board to use a PGA2350 which I was printing to use as a reference while I probed a few pins. But the pinout on the 'South' side was wrong.
Thankfully discovered before I sent to the fab...
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The second of my articles documenting creating a replacement Amstrad CPC gate array using a Raspberry Pi RP2350 microcontroller. This time I use a PIO, a DMA and an array of data to drive the six signals with fixed timings.
Lots of nerdy detail for anyone wants to learn what a Pico is capable of, or for those who want a better understanding of the DMAs.
https://bread80.com/2024/08/25/pico-garry-2350-part-2-fsigs-fixed-signals/
#PicoGarry #PicoGarry2350 #Amstrad #AmstradCPC #RP2350 #Pico #Pico2
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The second of my articles documenting creating a replacement Amstrad CPC gate array using a Raspberry Pi RP2350 microcontroller. This time I use a PIO, a DMA and an array of data to drive the six signals with fixed timings.
Lots of nerdy detail for anyone wants to learn what a Pico is capable of, or for those who want a better understanding of the DMAs.
https://bread80.com/2024/08/25/pico-garry-2350-part-2-fsigs-fixed-signals/
#PicoGarry #PicoGarry2350 #Amstrad #AmstradCPC #RP2350 #Pico #Pico2
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After wasting far too much time trying to configure a DMA properly I now have a 4MHz CPU clock on GPIO 0, with 50% duty cycle.
The meter doesn’t report a frequency on the 1MHz signals, but it does show a PWMed voltage. And it shows the 2MHz signals.
I’ll have to dig out the oscilloscope to test properly, but this should be the first stage complete.
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After wasting far too much time trying to configure a DMA properly I now have a 4MHz CPU clock on GPIO 0, with 50% duty cycle.
The meter doesn’t report a frequency on the 1MHz signals, but it does show a PWMed voltage. And it shows the 2MHz signals.
I’ll have to dig out the oscilloscope to test properly, but this should be the first stage complete.
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I now have the tools set up to develop for the RP2350, which means I can now start on the now Pico Garry.
This is the hardware I’m working with - a PGA2350 bodged to a USB socket.
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I now have the tools set up to develop for the RP2350, which means I can now start on the now Pico Garry.
This is the hardware I’m working with - a PGA2350 bodged to a USB socket.
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Time to resurrect the #PicoGarry project from it's cryogenic storage chamber.
Using the RP2350B I now have nine pins spare. The chip has a special block which be used for driving DVI (ie. HDMI) signals, so I'll tentatively reserve eight pins for that. And for the final one I can expand the two bit blue output to three. That'll give a bit more scope for tuning the three shades a CPC can output.
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Time to resurrect the #PicoGarry project from it's cryogenic storage chamber.
Using the RP2350B I now have nine pins spare. The chip has a special block which be used for driving DVI (ie. HDMI) signals, so I'll tentatively reserve eight pins for that. And for the final one I can expand the two bit blue output to three. That'll give a bit more scope for tuning the three shades a CPC can output.
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I’m taking a Quick Look at what a hypothetical next gen RP2040 would mean for the #PicoGarry. The current design uses two RP2040s, which then requires two ROMs, crystals, connectors etc.
A chip with about 40 GPIOs and another PIO or two would enable me to use a single chip.
5v tolerant pins would enable me to drop at between two and four glue chips.
That would make the project significantly easier to fit into a DIP40 package.
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I’m taking a Quick Look at what a hypothetical next gen RP2040 would mean for the #PicoGarry. The current design uses two RP2040s, which then requires two ROMs, crystals, connectors etc.
A chip with about 40 GPIOs and another PIO or two would enable me to use a single chip.
5v tolerant pins would enable me to drop at between two and four glue chips.
That would make the project significantly easier to fit into a DIP40 package.
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Cutting a long story short, I realised that I’ve reversed the pin order on the resistor DACs on the #PicoGarry. Oops.
That’s driven me to dig out an old board revision with trimmers to properly time the DACs - something I needed to do anyway.
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Cutting a long story short, I realised that I’ve reversed the pin order on the resistor DACs on the #PicoGarry. Oops.
That’s driven me to dig out an old board revision with trimmers to properly time the DACs - something I needed to do anyway.
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Picking up the #amstrad #picogarry project. I had to cut the reset line because the picos where being held in reset state.
The board has a small programmable logic chip. One of its functions is to translate the leading edge of the CPCs reset signal into a short pulse. This gives the picos time to boot before the CPC reset ends.
It turns out I had the output polarity wrong. It was giving a short high on the reset line. A quick reprogram and that’s issue 1 sorted 🙂
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Picking up the #amstrad #picogarry project. I had to cut the reset line because the picos where being held in reset state.
The board has a small programmable logic chip. One of its functions is to translate the leading edge of the CPCs reset signal into a short pulse. This gives the picos time to boot before the CPC reset ends.
It turns out I had the output polarity wrong. It was giving a short high on the reset line. A quick reprogram and that’s issue 1 sorted 🙂