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#disaggregation — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #disaggregation, aggregated by home.social.

  1. ALEXBSR @[email protected] ·

    Most CXL coverage collapses three separate things into one, which is why the technology reads as both imminent and permanently delayed.

    Expansion gives a single host extra CXL-attached memory as a second tier. It is in production at hyperscale — 768 GB of local DDR5-6400 alongside 256 GB of reclaimed DDR4-2400 per node, at 0.13 the cost per gigabyte of local DRAM, because those DIMMs were already bought.

    Pooling gives several hosts exclusive slices of a shared device, and does not require a switch: a multi-port device pools across whatever hosts plug into it. NSDI '26 measurements put multi-port paths at 260–300 ns against 490–600 ns switched.

    Sharing — many hosts on one region, coherent in hardware — is defined in CXL 3.0 and absent from shipping devices.

    The economics are the open question. Google researchers put switched break-even around 24 nodes. The same NSDI work finds sparse multi-port topologies save 3% to 5.4%. Topology decides.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Disaggregation #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure

    buysellram.com/blog/cxl-memory

    #cxl #computeexpresslink #memorypooling #servermemory #datacenter #disaggregation
  2. ALEXBSR @alexbsr ·

    Most CXL coverage collapses three separate things into one, which is why the technology reads as both imminent and permanently delayed.

    Expansion gives a single host extra CXL-attached memory as a second tier. It is in production at hyperscale — 768 GB of local DDR5-6400 alongside 256 GB of reclaimed DDR4-2400 per node, at 0.13 the cost per gigabyte of local DRAM, because those DIMMs were already bought.

    Pooling gives several hosts exclusive slices of a shared device, and does not require a switch: a multi-port device pools across whatever hosts plug into it. NSDI '26 measurements put multi-port paths at 260–300 ns against 490–600 ns switched.

    Sharing — many hosts on one region, coherent in hardware — is defined in CXL 3.0 and absent from shipping devices.

    The economics are the open question. Google researchers put switched break-even around 24 nodes. The same NSDI work finds sparse multi-port topologies save 3% to 5.4%. Topology decides.

    buysellram.com/blog/cxl-memory

    #cxl #computeexpresslink #memorypooling #servermemory #datacenter #disaggregation