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#computeexpresslink — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #computeexpresslink, aggregated by home.social.

  1. Nvidia Co-Founder: “Without Samsung and SK, There Would Be No AI Revolution”… Memory Evolves from ‘Storage’ to ‘Compute’

    Chris Malachowsky, co-founder of Nvidia and known as the ‘father of the GPU,’ lavished praise on South Korea’s…
    #EuropeSays #Korea #KR #SamsungElectronics #basedie #ChrisMalachowsky #ComputeExpressLink(CXL) #high-bandwidthmemory(HBM) #HotChips #NVIDIA #Processing-in-Memory(PIM) #Samsung #SKhynix #US-KoreaConference(UKC)
    europesays.com/korea/113632/

  2. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  3. Most CXL coverage collapses three separate things into one, which is why the technology reads as both imminent and permanently delayed.

    Expansion gives a single host extra CXL-attached memory as a second tier. It is in production at hyperscale — 768 GB of local DDR5-6400 alongside 256 GB of reclaimed DDR4-2400 per node, at 0.13 the cost per gigabyte of local DRAM, because those DIMMs were already bought.

    Pooling gives several hosts exclusive slices of a shared device, and does not require a switch: a multi-port device pools across whatever hosts plug into it. NSDI '26 measurements put multi-port paths at 260–300 ns against 490–600 ns switched.

    Sharing — many hosts on one region, coherent in hardware — is defined in CXL 3.0 and absent from shipping devices.

    The economics are the open question. Google researchers put switched break-even around 24 nodes. The same NSDI work finds sparse multi-port topologies save 3% to 5.4%. Topology decides.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Disaggregation #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure

    buysellram.com/blog/cxl-memory

  4. Most CXL coverage collapses three separate things into one, which is why the technology reads as both imminent and permanently delayed.

    Expansion gives a single host extra CXL-attached memory as a second tier. It is in production at hyperscale — 768 GB of local DDR5-6400 alongside 256 GB of reclaimed DDR4-2400 per node, at 0.13 the cost per gigabyte of local DRAM, because those DIMMs were already bought.

    Pooling gives several hosts exclusive slices of a shared device, and does not require a switch: a multi-port device pools across whatever hosts plug into it. NSDI '26 measurements put multi-port paths at 260–300 ns against 490–600 ns switched.

    Sharing — many hosts on one region, coherent in hardware — is defined in CXL 3.0 and absent from shipping devices.

    The economics are the open question. Google researchers put switched break-even around 24 nodes. The same NSDI work finds sparse multi-port topologies save 3% to 5.4%. Topology decides.

    buysellram.com/blog/cxl-memory

  5. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  6. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  7. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  8. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  9. Meta measures 43.7% of its servers as memory-capacity bound. They run out of RAM before they run out of cores, network, or storage.

    CXL is the standard meant to fix that, and it is further along than most coverage suggests in one direction and further behind in another. Expansion runs in production today. Pooling works on real hardware.

    #CXL #ComputeExpressLink #MemoryPooling #ServerMemory #DataCenter #Interconnect #DRAM #DDR4 #DDR5 #AIInfrastructure #tech

    buysellram.com/blog/cxl-memory

  10. Samsung, SK Hynix advance new memory layer to tackle AI scaling limits

    Samsung Electronics and SK hynix pushed to commercialize a new class of memory as artificial intelligence outgrew high-bandwidth…
    #EuropeSays #Korea #KR #SKHynix #AImemory #ComputeExpressLink #CXL #DRAM #high-bandwidthmemory #memorycapacity #memorymanagementtools #Samsung #SamsungElectronics #SK #SKhynix
    europesays.com/korea/92218/

  11. Ein weiterer Interconnect zur Anbindung von Speicher und Beschleunigern an CPUs wirft das Handtuch. IBMs OpenCAPI ist praktisch Geschichte.
    Neuer Branchenstandard: Intels CXL-Interconnect schluckt OpenCAPI
  12. Ein weiterer Interconnect zur Anbindung von Speicher und Beschleunigern an CPUs wirft das Handtuch. IBMs OpenCAPI ist praktisch Geschichte.
    Neuer Branchenstandard: Intels CXL-Interconnect schluckt OpenCAPI
  13. heise+ | PCIe und CXL: Wie schnelle Schnittstellen die Server-Architektur verändern

    Compute Express Link und PCIe 5.0 und 6.0 legen das Fundament für neue Serverkonzepte. Die Hardware solcher Maschinen lässt sich per Software zusammenschalten.
    PCIe und CXL: Wie schnelle Schnittstellen die Server-Architektur verändern
  14. heise+ | PCIe und CXL: Wie schnelle Schnittstellen die Server-Architektur verändern

    Compute Express Link und PCIe 5.0 und 6.0 legen das Fundament für neue Serverkonzepte. Die Hardware solcher Maschinen lässt sich per Software zusammenschalten.
    PCIe und CXL: Wie schnelle Schnittstellen die Server-Architektur verändern
  15. Durch hohe Transferraten, Switching, Cache-Kohärenz und weitere Funktionen ermöglichen PCIe 6.0 und CXL 2.0 neue Architekturen.
    PCI Express 6.0 und CXL 2.0 sollen Server umkrempeln
  16. Durch hohe Transferraten, Switching, Cache-Kohärenz und weitere Funktionen ermöglichen PCIe 6.0 und CXL 2.0 neue Architekturen.
    PCI Express 6.0 und CXL 2.0 sollen Server umkrempeln
  17. heise+ | Compute Express Link: Der Interconnect erklärt

    Memory- und Rechenressourcen aller Couleur will der neue Cache-kohärente Highspeed-Interconnect CXL quer über alle Server eines Racks verteilen.
    Compute Express Link: Der Interconnect erklärt