#cpczero — Public Fediverse posts

One challenge was the address bus between multiplexers and DRAM. I'm keep to preserve the layout from the prototype which with the CPU 'plexers at the top (U30, U31) and video 'plexers at the bottom (U40, U41) with RAM in a grid between them.

The obvious route would have been to fork the signals to run down each column of RAMs. But forks create reflections. And these are driven from either end so I'd end up with loops.

I ended up snaking them left then right. Not ideal but better.

#CPCZERO

Over the weekend I routed the main data bus between CPU, expansion port and RAM inputs etc., the RAM data bus, control signals to the expansion port, and signals within the RAM and multiplexers.

Today I've been adding the long distance signals between I/O and CPU and their origins, as well as those to the 'tape port' connector (to the cassette deck and speaker in a CPC).

#CPCZERO

Added:
CPU and ROM (top)
Expansion connector (bottom-right)
RAM (left)
Control logic (centre)

And routed the address lines.

There's more room left that I was expecting so I'm being less stingy with chip spacing. I'm hoping I don't regret that!

I found there was room to return to a ZIF socket for the ROM, which will be very helpful!

I'm doing a lot of pin remapping to ease the routing.

#CPCZERO #Amstrad_cpc

Next to see why Kicad isn't drawing the board outline. It turns out the footprint for the audio jack include board edges. It's a low profile socket with the port below board level. But Amstrad mounted the socket slightly forward of the board, cutting some mounting lugs in half.

I've tweaked the footprint to remove the board edges, and added some 'nibbles' for the mounting lugs.

#CPCZERO

After far too mush hassle the printer port is now routed.

Amstrad schematics claim it's a 36-way connector, even in a 6128. It's not. It's 34! That gives an off-by-one numbering error on the rear pins. And there's few discrepancies between schematics and PCBs, largely over which pins are grounded. I've copied from an actual machine.

I've also tightened up the gaps between traces for joystick and printer. They're slow signals and I'd prefer board space for other things.

#CPCZERO #Kicad

On the #CPCZERO project I've been debating whether to finish designing all the video and interrupt circuitry or whether to do a board as-is with connectors to add video on a daughter board later. The latter potentially needs less board revisions but would add a lot of time while I get the remaining design finished. So I'm going with the first option and starting board layout.

The other unknown is how much space I'll need. But I know things are going to be tight.

1/2

With the RAM sorted I’m moving onto the 6845 CRTC. One fly in the ointment here: it’s I/O cycle maxes out at 1MHz. I’m running the 6502 at 2MHz. I think the easiest solution is probably to slow the CPU to 1MHz when accessing the 6845 but that will mean a few changes to the sequencer.

I note this is the solution used by the BBC Micro (which also uses a 2MHz 6502 and 6845).

#CPCZERO

Old school DRAMs have a lot of timing requirements. I’ve been validating output from the #CPCZERO sequencer prototype against them - and everything checks out 🙂

Comments in my notes are where the timings depend on other components, such as the multiplexers.

#mos6502 #Homebrewcomputer #amstrad

Adding basic 6502 emulation to my gate level logic simulator for the CPC ZERO project. I'm only adding emulation of the various cycle types to validate the rest of the system. Here it's raising an error because the RESET pulse is shorter than the 6502 requires.

#Amstrad #CPCZERO #Kicad #Delphi

The CPC ZERO project has been stalled pending some updates to my gate level simulator. I needed it to be able to handle gate delays so I could properly test the sequencer circuit. Today I've been adding necessary code. All the timing data is currently hard coded into the simulator, rather than loaded from a file, but that's enough for now.

I found the circuit was starting with the shift registers out of phase but a tweak to the reset circuit appears to have fixed things.

#CPCZERO #AmstradCPC

Pixel generation is a lot more fun to work on. It requires parallel in, parallel out shift registers. I thought they'd be difficult to find but the 74LS164 is still available. It can even shift either direction but I don't need that functionality.

#CPCZERO

I needed to do something calming today. Entering schematics is often calming. So I been working on the DRAMs and multiplexers. But doing everything eight times is not the calming I was looking for.

I still have to assign address lines to DRAM pins but that will depend on board layout so I'll leave for later. The same for address lines to the multiplexers. That requires more concentration than I can muster today.

#CPCZERO

A rework of the sequencer circuit. I was using the state of the shift registers to inject the initial 1 pulse into the shift registers. However the LS164s are too slow for that to work. That meant the two shift registers might start up out of phase.

I've added a fast 74S74 to generate a reset pulse from /RESET and 16MHZ to guaranteed the phasing. But the sequencer needs to generate CPU clocks during reset, so a second S74 acts as an edge detects ~RESET down to a single 16MHz cycle.

#CPCZERO

And the project file so far for the CPC ZERO.

The CAD files don't give enough detail on the oscillator so this needs to be specified in the project file with the AddOscillator command which has parameters for name, frequency and the net to drive.

#CPCZERO #Smorgasbord

Playing with sequencer circuits in Logisim Evolution. This looks like it's doing the job.

For memory control I need to trigger actions on both the rising and falling edge of the 16MHz system clock. So I'm using two shift registers, one clocked on the rising edge and one on the falling edge.

It's then a case of gating signals off the eight possible steps. Flip-flips drive the video vs CPU selector (the 2MHz CPU clock), the 1MHz CRTC clock, and gate CAS.

#CPCZERO

Doing some testing on the CPC ZERO. I’ve coded a loop which takes 9 clocks and includes one write cycle. I found a few bad solder joints on the lines between the ROM ZIF socket and its header pins.

After resoldering them I now get the output below. Yellow is clock, blue is R/W. However it’s easy to knock it off course into what looks like constantly retriggering BRK cycles (unused memory addresses are filled with $00, the BRK opcode).

Hopefully better power input will fix this.

#CPCZERO

Boning up on the 6502 boot sequence and realising I need to change the memory map slightly. I was going to put video memory from C000 to FFFF but that won’t play nicely with the interrupt vectors.

The best solution looks to be putting video memory between 8000 and BFFF. The downside is how this splits available RAM.

IO can slide up from the page at BF00 to C000.

#CPCZERO

Prepping for the next stage on the CPC ZERO. New sockets and header added.

#CPCZERO

Using Logisim Evolution to validate (and fix) some circuits for the CPC ZERO.

I haven't used Logisim for a could of years but it's now feeling very solid and user friendly. I'd highly recommend it.

#CPCZERO

The first stage of my CPC ZERO build - a hypothetical 6502 based Amstrad CPC taking inspiration from the prototype 6502 board and the final Z80 based CPC464.

I'm using period appropriate hardware, wire wrapping the build, and solving design challenges the way they had to in the eighties.

In this zero-th part I state my design goals, choose a build method and build out the CPU and ROM.

https://bread80.com/2024/11/01/cpc-zero-part-0-intro-cpu-and-rom/

#CPCZERO #Amstrad #MOS6502 #WireWrapping