#epyc9355p — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #epyc9355p, aggregated by home.social.
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#AMD’s #EPYC9355P: Inside a 32 Core #Zen5 #Server Chip, where per-core performance still matters
AMD uses eight #CPU dies (CCDs) to house those 32 cores. Each #CCD only has four cores enabled out of the eight physically present, but still has its full 32 MB of L3 cache usable, a high cache to core count.
Article Covers:
Memory Subsystem and NUMA Characteristics
A Look into GMI-Wide
SPEC CPU2017
https://chipsandcheese.com/p/amds-epyc-9355p-inside-a-32-coreGreat Article!
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#AMD’s #EPYC9355P: Inside a 32 Core #Zen5 #Server Chip, where per-core performance still matters
AMD uses eight #CPU dies (CCDs) to house those 32 cores. Each #CCD only has four cores enabled out of the eight physically present, but still has its full 32 MB of L3 cache usable, a high cache to core count.
Article Covers:
Memory Subsystem and NUMA Characteristics
A Look into GMI-Wide
SPEC CPU2017
https://chipsandcheese.com/p/amds-epyc-9355p-inside-a-32-coreGreat Article!
-
#AMD’s #EPYC9355P: Inside a 32 Core #Zen5 #Server Chip, where per-core performance still matters
AMD uses eight #CPU dies (CCDs) to house those 32 cores. Each #CCD only has four cores enabled out of the eight physically present, but still has its full 32 MB of L3 cache usable, a high cache to core count.
Article Covers:
Memory Subsystem and NUMA Characteristics
A Look into GMI-Wide
SPEC CPU2017
https://chipsandcheese.com/p/amds-epyc-9355p-inside-a-32-coreGreat Article!
-
#AMD’s #EPYC9355P: Inside a 32 Core #Zen5 #Server Chip, where per-core performance still matters
AMD uses eight #CPU dies (CCDs) to house those 32 cores. Each #CCD only has four cores enabled out of the eight physically present, but still has its full 32 MB of L3 cache usable, a high cache to core count.
Article Covers:
Memory Subsystem and NUMA Characteristics
A Look into GMI-Wide
SPEC CPU2017
https://chipsandcheese.com/p/amds-epyc-9355p-inside-a-32-coreGreat Article!