#avx10 — Public Fediverse posts

Hard to believe, but 2 years ago to the day I gave my @easybuild TechTalk on #AVX10 and the history of #SIMD on x86!

Very fun looking back on the slides (available here: https://github.com/FCLC/Talks/blob/main/AVX10forHPC_small_v2.pdf)

And thinking back on the context that talk was written in.

Namely at the then existing AVX10.N/M proposed spec, where M could be {128,256,512}

#asm #AVX512 #AVX10

Hard to believe, but 2 years ago to the day I gave my @easybuild TechTalk on #AVX10 and the history of #SIMD on x86!

Very fun looking back on the slides (available here: https://github.com/FCLC/Talks/blob/main/AVX10forHPC_small_v2.pdf)

And thinking back on the context that talk was written in.

Namely at the then existing AVX10.N/M proposed spec, where M could be {128,256,512}

#asm #AVX512 #AVX10

LETS GOOOOO

#Intel listened! No more ambiguity, no more questioning, 128 bit only implementations are no longer valid for #AVX10!

A massive thanks to the Intel ISA folks!

And a major thanks to @chipsandcheese for giving me a platform to express my concerns on the spec!

For those wanting to read the updated spec, it’s here: https://cdrdv2.intel.com/v1/dl/getContent/828964?fileName=355989-intel-avx10.1-spec.pdf

And for those interested in the article asking for this, it’s available here: https://chipsandcheese.com/2023/10/11/avx10-128-is-a-silly-idea-and-should-be-completely-removed-from-the-specification/

#HPC #AVX #x86 #x86_64

LETS GOOOOO

#Intel listened! No more ambiguity, no more questioning, 128 bit only implementations are no longer valid for #AVX10!

A massive thanks to the Intel ISA folks!

And a major thanks to @chipsandcheese for giving me a platform to express my concerns on the spec!

For those wanting to read the updated spec, it’s here: https://cdrdv2.intel.com/v1/dl/getContent/828964?fileName=355989-intel-avx10.1-spec.pdf

And for those interested in the article asking for this, it’s available here: https://chipsandcheese.com/2023/10/11/avx10-128-is-a-silly-idea-and-should-be-completely-removed-from-the-specification/

#HPC #AVX #x86 #x86_64

#Intel implemented a change I wanted in #AVX10 and that’s like? Really cool?

Seeing MPI wrappers for the llvm Intel compilers based on a previous suggestion was already really cool, but now seeing the core ISA spec have a change is just…Wow

https://cdrdv2-public.intel.com/795593/355989-intel-avx10-spec.pdf

AVX10 rev2 #HPC

#Intel implemented a change I wanted in #AVX10 and that’s like? Really cool?

Seeing MPI wrappers for the llvm Intel compilers based on a previous suggestion was already really cool, but now seeing the core ISA spec have a change is just…Wow

https://cdrdv2-public.intel.com/795593/355989-intel-avx10-spec.pdf

AVX10 rev2 #HPC

Thanks to all who attended the Easy build tech talk on #AVX10!

Will share the recording once available

Thanks to all who attended the Easy build tech talk on #AVX10!

Will share the recording once available

It’s donnnnnnne!

https://chipsandcheese.com/2023/10/11/avx10-128-is-a-silly-idea-and-should-be-completely-removed-from-the-specification/

Here’s a medium length article that introduces the concept of AVX10, its history, and asks intel to explicitly remove part of it!

#avx10 #AVX512 #HPC

It’s donnnnnnne!

https://chipsandcheese.com/2023/10/11/avx10-128-is-a-silly-idea-and-should-be-completely-removed-from-the-specification/

Here’s a medium length article that introduces the concept of AVX10, its history, and asks intel to explicitly remove part of it!

#avx10 #AVX512 #HPC

Wondering if the Intel #OpenCL CPU runtime will ever get proper FP16 support, including the #F16c extensions and #AVX512 Extensions :/

Maybe when the framework gets #AVX10 support?

Wondering if the Intel #OpenCL CPU runtime will ever get proper FP16 support, including the #F16c extensions and #AVX512 Extensions :/

Maybe when the framework gets #AVX10 support?

Friendly reminder for @fclc’s EasyBuild Tech Talk "AVX10 for HPC - A reasonable solution to the 7 levels of AVX-512 folly" which is scheduled for Fri 13 Oct 2023 at 13:30 UTC.
More info via https://easybuild.io/tech-talks/008_avx10.html

#HPC #AVX10

Friendly reminder for @fclc’s EasyBuild Tech Talk "AVX10 for HPC - A reasonable solution to the 7 levels of AVX-512 folly" which is scheduled for Fri 13 Oct 2023 at 13:30 UTC.
More info via https://easybuild.io/tech-talks/008_avx10.html

#HPC #AVX10

Did Toms get it wrong or did they just leak that Meteor lake/Crestmont is getting #AVX10/256?

https://tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14

I don't see anything in the slides they reference about AVX10, only the VEX encoded versions of VNNI, IFMA etc.

HT: @st01014

Did Toms get it wrong or did they just leak that Meteor lake/Crestmont is getting #AVX10/256?

https://tomshardware.com/news/intel-details-core-ultra-meteor-lake-architecture-launches-december-14

I don't see anything in the slides they reference about AVX10, only the VEX encoded versions of VNNI, IFMA etc.

HT: @st01014

Hi friends! Very excited to announce that I'll be giving an @easybuild Tech Talk on the 13th of October on #AVX10!

The Talk is titled "AVX10 for HPC:
A reasonable solution to the 7 levels of AVX-512 folly"

Registration is free, all #x86, #AVX, #AVX512, #SIMD, and #HPC experience levels welcome!

The page is here: https://easybuild.io/tech-talks/008_avx10.html

And you can register here! https://event.ugent.be/registration/ebtechtalk008avx10

Hi friends! Very excited to announce that I'll be giving an @easybuild Tech Talk on the 13th of October on #AVX10!

The Talk is titled "AVX10 for HPC:
A reasonable solution to the 7 levels of AVX-512 folly"

Registration is free, all #x86, #AVX, #AVX512, #SIMD, and #HPC experience levels welcome!

The page is here: https://easybuild.io/tech-talks/008_avx10.html

And you can register here! https://event.ugent.be/registration/ebtechtalk008avx10

@fclc Going through each of #AVX10 features (e.g more reg registers, conditional instructions...) compared to previous x86 generation, and show case impact on performance and ASM low level codegen with multiple micro-benchmarks/examples, and highlight how existing code is benefiting these new features

@fclc Going through each of #AVX10 features (e.g more reg registers, conditional instructions...) compared to previous x86 generation, and show case impact on performance and ASM low level codegen with multiple micro-benchmarks/examples, and highlight how existing code is benefiting these new features

Hi friends! Say someone was going to give a talk on the new #AVX10 extensions in the context of #HPC, what would you want to hear about?

Definitely not outlining under working title
"AVX10 for HPC, x86_64 returns to Sanity*"
DMs/replies with comments/suggestions appreciated 😊

Hi friends! Say someone was going to give a talk on the new #AVX10 extensions in the context of #HPC, what would you want to hear about?

Definitely not outlining under working title
"AVX10 for HPC, x86_64 returns to Sanity*"
DMs/replies with comments/suggestions appreciated 😊

Something doesn't fit in the register article covering AVX10.

An #Intel fellow comments that AVX10 requires 256 bit or larger implementations, yet there's an *explicit* carve out in the spec for 128 bit implementations, & that carve out means that you *must* plan for AVX10.N/128, instead of having a true baseline of AVX10.N/256

the specific passage is "[... ] 256 bit instructions will be the minimum width required by the AVX10 instruction set."

https://www.theregister.com/2023/08/15/avx10_intel_interviews/
#HPC #AVX512 #avx10

Something doesn't fit in the register article covering AVX10.

An #Intel fellow comments that AVX10 requires 256 bit or larger implementations, yet there's an *explicit* carve out in the spec for 128 bit implementations, & that carve out means that you *must* plan for AVX10.N/128, instead of having a true baseline of AVX10.N/256

the specific passage is "[... ] 256 bit instructions will be the minimum width required by the AVX10 instruction set."

https://www.theregister.com/2023/08/15/avx10_intel_interviews/
#HPC #AVX512 #avx10

Intel #AVX10 is a new #ISA that includes "all the richness" of #AVX512 and additional features/capabilities while being able to work for both P/E cores. Intel says AVX10 will be "the vector ISA of choice" moving forward.Very exciting from hardware perspective with Intel's #opensource track record around new ISA support it means we'll likely start seeing software enablement preparations begin soon so that everything is upstream and ready by time supported processors ship.
https://www.phoronix.com/news/Intel-AVX10

Intel #AVX10 is a new #ISA that includes "all the richness" of #AVX512 and additional features/capabilities while being able to work for both P/E cores. Intel says AVX10 will be "the vector ISA of choice" moving forward.Very exciting from hardware perspective with Intel's #opensource track record around new ISA support it means we'll likely start seeing software enablement preparations begin soon so that everything is upstream and ready by time supported processors ship.
https://www.phoronix.com/news/Intel-AVX10