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263 results for “bread80”
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I want to see if I can make my #Enterprise64 keyboard a bit less ‘squidgy’. I’ve bought a selection of the thinnest tactile switches I can find to experiment with. The switches here run from 0.8mm to 2.5mm.
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I want to see if I can make my #Enterprise64 keyboard a bit less ‘squidgy’. I’ve bought a selection of the thinnest tactile switches I can find to experiment with. The switches here run from 0.8mm to 2.5mm.
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I want to see if I can make my #Enterprise64 keyboard a bit less ‘squidgy’. I’ve bought a selection of the thinnest tactile switches I can find to experiment with. The switches here run from 0.8mm to 2.5mm.
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I want to see if I can make my #Enterprise64 keyboard a bit less ‘squidgy’. I’ve bought a selection of the thinnest tactile switches I can find to experiment with. The switches here run from 0.8mm to 2.5mm.
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Having a play with the video chip on the #Enterprise64. This is a demo from the manual which creates a text video window in the centre of the screen. The original BASIC text window is still there ‘underneath’ it. Note that the central lines of the BASIC window are still there, just being masked out by the second window.
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Having a play with the video chip on the #Enterprise64. This is a demo from the manual which creates a text video window in the centre of the screen. The original BASIC text window is still there ‘underneath’ it. Note that the central lines of the BASIC window are still there, just being masked out by the second window.
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Having a play with the video chip on the #Enterprise64. This is a demo from the manual which creates a text video window in the centre of the screen. The original BASIC text window is still there ‘underneath’ it. Note that the central lines of the BASIC window are still there, just being masked out by the second window.
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Having a play with the video chip on the #Enterprise64. This is a demo from the manual which creates a text video window in the centre of the screen. The original BASIC text window is still there ‘underneath’ it. Note that the central lines of the BASIC window are still there, just being masked out by the second window.
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I finally have the Flan wired up to the RGBToHDMI. Still some sparklies on screen but otherwise looking fantastic.
And having a little explore of the BASIC. Recursive function definitions is cool. The wordiness isn’t so great though. Feels a bit like interpreted COBOL.
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I finally have the Flan wired up to the RGBToHDMI. Still some sparklies on screen but otherwise looking fantastic.
And having a little explore of the BASIC. Recursive function definitions is cool. The wordiness isn’t so great though. Feels a bit like interpreted COBOL.
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I finally have the Flan wired up to the RGBToHDMI. Still some sparklies on screen but otherwise looking fantastic.
And having a little explore of the BASIC. Recursive function definitions is cool. The wordiness isn’t so great though. Feels a bit like interpreted COBOL.
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I finally have the Flan wired up to the RGBToHDMI. Still some sparklies on screen but otherwise looking fantastic.
And having a little explore of the BASIC. Recursive function definitions is cool. The wordiness isn’t so great though. Feels a bit like interpreted COBOL.
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Checking the back of the #RP2350 #Pico-2 datasheet:
THE GPIOS ARE 5V TOLERANT !!!
Image 1: Specs for 'FT' (fault tolerant) pins.
Image 2: Pin type definitions.
Image 3: Listing of GPIO pins (not all shown 'cos there's far too many).
(PS The rating for the Analogue/Digital pins which can be routed to ADCs is unclear, but I'm expecting they have the same ratings).
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Checking the back of the #RP2350 #Pico-2 datasheet:
THE GPIOS ARE 5V TOLERANT !!!
Image 1: Specs for 'FT' (fault tolerant) pins.
Image 2: Pin type definitions.
Image 3: Listing of GPIO pins (not all shown 'cos there's far too many).
(PS The rating for the Analogue/Digital pins which can be routed to ADCs is unclear, but I'm expecting they have the same ratings).
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Checking the back of the #RP2350 #Pico-2 datasheet:
THE GPIOS ARE 5V TOLERANT !!!
Image 1: Specs for 'FT' (fault tolerant) pins.
Image 2: Pin type definitions.
Image 3: Listing of GPIO pins (not all shown 'cos there's far too many).
(PS The rating for the Analogue/Digital pins which can be routed to ADCs is unclear, but I'm expecting they have the same ratings).
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Checking the back of the #RP2350 #Pico-2 datasheet:
THE GPIOS ARE 5V TOLERANT !!!
Image 1: Specs for 'FT' (fault tolerant) pins.
Image 2: Pin type definitions.
Image 3: Listing of GPIO pins (not all shown 'cos there's far too many).
(PS The rating for the Analogue/Digital pins which can be routed to ADCs is unclear, but I'm expecting they have the same ratings).
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I think that's enough routing for one day. This is the second page of instruction decoding. Here we have:
* HALT opcodes - there's three of them, &00, &01, &ff. I don't know why they felt the need for three. Those octal NANDs are one gate per chip which. But &ff would, otherwise, decode to LD (HL),(HL). Z80 peoples will be proud of that.
* Some branching stuff.
* Some general stuff.
* Shift and I/O stuff.(I know those comments aren't helpful. I'm tired).
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If my ordering for this seems a little random it's because I'm following Kicads page numbering of the schematics. But I'm skipping forward to the instruction register because it produces a tonne of control signals which trace across the board.
Instructions are grouped by bits 7 and 6 of the bytecode. Depending on the opcode bits 4,3,2 and 2,1,0 encode the destination and source registers respectively.
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BTW if you look at the bits of the opcode which are encoding the flags and compare then to the equivalent Z80 opcodes you'll notice they're identical. There are, of course, a lot of similarities between the 2200 and it's great grandchild.
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This part of the circuit uses OC gates to select whether a branch needs to be taken. Z35A and Z35D will output zero if the flag matches the if true/if false specified by IR5. In IR2 is high we have an unconditional branch and, in that case, Z2A always drives the signal low.
Examine the circuit and you'll notice it's actually functioning as an OR gate (but with inverted logic). Using a single resistor helps reduce the chip count.
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Flags and branch control. This is a nice, easy to understand circuit. It starts with computing the zero, sign and parity flags. Since we have a 1-bit ALU the sign and parity flags are re-evaluated for each bit. Sign flag is just bit 7 of the result. Carry flag circuit is on another page.
IRn are raw bits of the opcode from the instruction register. A multiplexer IC uses IR3 and 4 select a flag to test. IR5 selects for condition true or condition false.
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Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
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And the mostly routed address related sections of the board. I've marked the 7 multiplexer ICs with red and sorted the silkscreen labels for the other chips.
There's an enjoyable symmetry to those multiplexers - if you ignore Z113.
Routing for now is a case of getting everything connected. I'll tidy later. And I'm leaving space down the middle of ICs to route power and ground. I've never tried this before. I'm hoping it'll be easier than trying to squeeze them in later.
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Next up, H and L registers. Probably the simplest schematic of the lot.
These shift registers output to the /DATA bus via an open collector NAND gate. The /DATA line takes output from all the registers, the memory cards, and the tape board - which reads a file on reboot.
Inverters (top left) output to
1) the REG_DATA line which is used as input by the B,C,D,E,H,L registers,
2) the DATA line which is input to everywhere else (IR, ALU, temp addr reg) -
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
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You'll notice I've rotated the board 180 degrees in the editor.
Routing it this way is helping me to see where functionality lives. Given the natural viewing angle will be from the front (memory cards at the rear) rotating it now saves me having to relearn the map later.
It is, however, a total mind freak to now see everything upside down.
Another benefit to this: the first page of the schematic is the control stuff. So most of the long, winding, traces should now be done.
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I'm finding the best way to route this is by working through the schematics. The other way, starting with Z1 was challenging due to the length of the traces and the number of destinations.
Doing it this way I can quickly see from the schematic if there's just one or two other pins to visit. That probably sounds long winded but it works form my brain.
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Footprints imported to the PCB designer. Not actually as scary as I was expecting. Let the fun begin...
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Adding a page of spare units, based off the table on the original schematics, but the design checker doesn't like it.
So, the original is hard to read, and I've not double checked what I've copied, but it clearly shows Z95 with some spare units. But Z95 is one of the RAM chips making up the stack. So this table is definitely error prone.