#datapoint — Public Fediverse posts
Live and recent posts from across the Fediverse tagged #datapoint, aggregated by home.social.
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Regression learns from examples.
House size → house price.
Repeated many times.Patterns don’t come from one data point — they emerge from many.
#manytimes #house #houseprice #timepatterns #datapoint #examples
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Week 15 Data Dump: Can Philip Rivers save Colts fantasy stars? + Identifying true LEAGUE WINNERS https://www.rawchili.com/nfl/588786/ #Chargers #Colts #DataPoint #Football #JaxsonDart #JonathanTaylor #MattHarmon #MichaelWilson #NFL #PhilipRivers #RayGarvin #YahooFantasy
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Week 14 Data Dump: Can we trust these WRs and RBs in the push for the fantasy PLAYOFFS?! https://www.rawchili.com/nfl/572079/ #ChubaHubbard #DataPoint #EmekaEgbuka #Football #JamesonWilliams #MattHarmon #NFL #RayGarvin #Steelers #YahooFantasy
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The key switches I chose for the Datapoint 2200 keyboard required a plate so I made one up. Done as a PCB it’s not cheap but the Matt black finish works really well.
The only issue is that it slightly obstructs a couple of capacitors 🙁
I still need to source the hardware to properly mount it to the keyboard.
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The key switches I chose for the Datapoint 2200 keyboard required a plate so I made one up. Done as a PCB it’s not cheap but the Matt black finish works really well.
The only issue is that it slightly obstructs a couple of capacitors 🙁
I still need to source the hardware to properly mount it to the keyboard.
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Top row numbers can be shifted and keypad numbers can't. Both share an edge detector circuit and multiplexer 'line'. Top row key short to ground whereas keypad key have an SIO (or S10) signal. The keyboard logic board uses an analogue edge detector with 74121 pulse generator.
On the Pico I'm handling this by driving the SIO line low. When a keypress is detected I drive it high. If the keypress is still detectable then it's a top row key. If not then keypad.
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Top row numbers can be shifted and keypad numbers can't. Both share an edge detector circuit and multiplexer 'line'. Top row key short to ground whereas keypad key have an SIO (or S10) signal. The keyboard logic board uses an analogue edge detector with 74121 pulse generator.
On the Pico I'm handling this by driving the SIO line low. When a keypress is detected I drive it high. If the keypress is still detectable then it's a top row key. If not then keypad.
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The #Datapoint2200 keyboard PCBs have arrived and they look fantastic. Somehow larger than I expected, and very imposing.
#datapoint #ttlcomputer #vintagecomputer #retroconputer #mechanicalkeyboard
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The #Datapoint2200 keyboard PCBs have arrived and they look fantastic. Somehow larger than I expected, and very imposing.
#datapoint #ttlcomputer #vintagecomputer #retroconputer #mechanicalkeyboard
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I've now added some photos to the repository (link in previous toot). Not the best quality but there's now something to look at.
Here's a couple of those for the Decoder PCB. There are more in the repository itself.
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I've now added some photos to the repository (link in previous toot). Not the best quality but there's now something to look at.
Here's a couple of those for the Decoder PCB. There are more in the repository itself.
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I've just pushed a very long overdue update to my Datapoint 2200 repository.
New stuff includes schematics for video, keyboard and keyboard logic.
I've added a fair few LEDs to the processor PCB for most of the main registers, but I need to analyse which other signals deserve to have them.
I also need to add some photos and PCB renders to the readme.
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I've just pushed a very long overdue update to my Datapoint 2200 repository.
New stuff includes schematics for video, keyboard and keyboard logic.
I've added a fair few LEDs to the processor PCB for most of the main registers, but I need to analyse which other signals deserve to have them.
I also need to add some photos and PCB renders to the readme.
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#Datapoint 2200: I have the memory cards designed and assembled but no memory chips. My plan is to add a 'backpack' board using modern parts.
Each card uses 32x 512 bit shift memory chips. The best modern option is probably 512 bit FIFOs and tie the outputs back to the inputs to recirculate data.
You can get 9-bit or 18-bit wide chips but every bit is read and written together. So you need a multiplexer on each bit to select new data or recirculate.
🧵
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#Datapoint 2200: I have the memory cards designed and assembled but no memory chips. My plan is to add a 'backpack' board using modern parts.
Each card uses 32x 512 bit shift memory chips. The best modern option is probably 512 bit FIFOs and tie the outputs back to the inputs to recirculate data.
You can get 9-bit or 18-bit wide chips but every bit is read and written together. So you need a multiplexer on each bit to select new data or recirculate.
🧵
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What's the main challenge in assembling old code on a modern(ish) assembler? The old assemblers only consider the first few letters of a mnemonic significant. The 8008 has an INC opcode. My assembler has an INCLUDE directive.
(The old code doesn't use INCLUDE, but I need to import symbols from other files. The easy way is to write public symbols to a file in suitable format for an INCLUDE).
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What's the main challenge in assembling old code on a modern(ish) assembler? The old assemblers only consider the first few letters of a mnemonic significant. The 8008 has an INC opcode. My assembler has an INCLUDE directive.
(The old code doesn't use INCLUDE, but I need to import symbols from other files. The easy way is to write public symbols to a file in suitable format for an INCLUDE).
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I wrote a Z80 assembler a few years ago. Thankfully I subclassed out the Z80 specific stuff. I've been updating it for Datapoint mnemonics and syntax.
I've also typed in the #Datapoint operating system listing from the Programmers Manual (46 pages. Nothing to a child of the 80s).
I'm now working through the files to get them to assemble. Currently there's a circular reference to resolve (comment out on first build), a couple of directives to add and an opcode which doesn't officially exist.
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I wrote a Z80 assembler a few years ago. Thankfully I subclassed out the Z80 specific stuff. I've been updating it for Datapoint mnemonics and syntax.
I've also typed in the #Datapoint operating system listing from the Programmers Manual (46 pages. Nothing to a child of the 80s).
I'm now working through the files to get them to assemble. Currently there's a circular reference to resolve (comment out on first build), a couple of directives to add and an opcode which doesn't officially exist.
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Now to get memory writes working in the Datapoint simulator. There's a /MEMORY_WRITE_READY input which needs to be driven. The circuit for this is on the keyboard decoder PCB.
Unconnected to the rest of that board, except for a POR output. Not the first bit of circuit I've found spilled onto a different board.
The circuit drives the /MEM_WRITE_READY line while the hardware bootloader reads data from tape. I can just glue it high for now.
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Now to get memory writes working in the Datapoint simulator. There's a /MEMORY_WRITE_READY input which needs to be driven. The circuit for this is on the keyboard decoder PCB.
Unconnected to the rest of that board, except for a POR output. Not the first bit of circuit I've found spilled onto a different board.
The circuit drives the /MEM_WRITE_READY line while the hardware bootloader reads data from tape. I can just glue it high for now.
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'Clear the carry tiggle'.
I think they meant to say 'toggle', although twice suggests it may be intentional.
The documentation usually refers to 'flip-flops' as opposed to 'flags', or 'toggles'.
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'Clear the carry tiggle'.
I think they meant to say 'toggle', although twice suggests it may be intentional.
The documentation usually refers to 'flip-flops' as opposed to 'flags', or 'toggles'.
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I like how the #Datapoint assembler has pseudo instructions to load a 16-bit value into the H, L and D, E registers. Strangely there's no equivalent for B, C.
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I like how the #Datapoint assembler has pseudo instructions to load a 16-bit value into the H, L and D, E registers. Strangely there's no equivalent for B, C.
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I'm spending the afternoon running through the #Datapoint2200 instruction set in the simulator to test everything.
So far, loads working, as are all the ALU operations, including the two shifts.
I've done my first ever use of the stack (with CALL and RETurn) which checks out okay.
Pretty much the only thing left to test is writes to memory. I'm fairly sure there's still a bug in the simulator code due to time when I'm clocking the memory bits. Should be a simple fix.
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I'm spending the afternoon running through the #Datapoint2200 instruction set in the simulator to test everything.
So far, loads working, as are all the ALU operations, including the two shifts.
I've done my first ever use of the stack (with CALL and RETurn) which checks out okay.
Pretty much the only thing left to test is writes to memory. I'm fairly sure there's still a bug in the simulator code due to time when I'm clocking the memory bits. Should be a simple fix.
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Long strings? What craziness is this!
(From the #Datapoint2200 Programmers Manual. The STATH library manipulates numbers stored in strings ('numeric strings')). In ASCII.
(I can't image how much that must have hammered numeric performance. And the Datapoint wasn't exactly the fastest machine to start with.)
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Long strings? What craziness is this!
(From the #Datapoint2200 Programmers Manual. The STATH library manipulates numbers stored in strings ('numeric strings')). In ASCII.
(I can't image how much that must have hammered numeric performance. And the Datapoint wasn't exactly the fastest machine to start with.)
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Want to learn how to build and foster a strong, healthy #DataCulture in your organization?
Then you should definitely attend my session called "The #DataDojo: A #PowerBI #CommunityOfPractice" at #DataPointPrague2024 (May 30-31, #Prague, #CzechRepublic).
Register here: https://datapointprague.cz
Shout out to @StepanResl and #DataBrothers for organizing this conference, it's gonna be a real banger!
#MicrosoftFabric #DataPointPrague #DataPoint #DataLiteracy #DataGovernance #CenterOfExcellence #DataDriven #SoftSkills #CitizenDataAnalysts #SelfServiceAnalytics #SelfServiceBI
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Want to learn how to build and foster a strong, healthy #DataCulture in your organization?
Then you should definitely attend my session called "The #DataDojo: A #PowerBI #CommunityOfPractice" at #DataPointPrague2024 (May 30-31, #Prague, #CzechRepublic).
Register here: https://datapointprague.cz
Shout out to @StepanResl and #DataBrothers for organizing this conference, it's gonna be a real banger!
#MicrosoftFabric #DataPointPrague #DataPoint #DataLiteracy #DataGovernance #CenterOfExcellence #DataDriven #SoftSkills #CitizenDataAnalysts #SelfServiceAnalytics #SelfServiceBI
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I/O on the #Datapoint 2200 (as I'm understanding it) :
The instructions are similar to the i8008. Bits 4 to 1 of the bytecode code the I/O port. 32 addresses, but the first 8 are inputs, mapped to instructions IN 0..7. The remaining 24 are outputs mapped to instructions OUT 0..23.
The Datapoint uses the instruction EX for outputs (short for external IIRC)). Rather than port numbers it uses names. The first 8 are generic:
EX ADR
EX STATUS
EX DATA
EX WRITE
EX COM1 though EX COM4
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I/O on the #Datapoint 2200 (as I'm understanding it) :
The instructions are similar to the i8008. Bits 4 to 1 of the bytecode code the I/O port. 32 addresses, but the first 8 are inputs, mapped to instructions IN 0..7. The remaining 24 are outputs mapped to instructions OUT 0..23.
The Datapoint uses the instruction EX for outputs (short for external IIRC)). Rather than port numbers it uses names. The first 8 are generic:
EX ADR
EX STATUS
EX DATA
EX WRITE
EX COM1 though EX COM4
🧵 -
I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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Returning to the #Datapoint simulator to try and fix a thorny issue that's been eluding me for a while.
The four chips at the bottom are '193 counters which normally house the program counter. Above are a row of '153 4-to-1 multiplexers. These can load an address from the stack, the H, L registers or the temp address register (for inline jump, call addresses).
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Returning to the #Datapoint simulator to try and fix a thorny issue that's been eluding me for a while.
The four chips at the bottom are '193 counters which normally house the program counter. Above are a row of '153 4-to-1 multiplexers. These can load an address from the stack, the H, L registers or the temp address register (for inline jump, call addresses).
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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@danlyke @thomasfuchs I actually did a fun month-long alternative college class in 1986 that involved a daily comprehensive side-by-side read-through of the NYT and the Wall Street Journal, followed by class discussion over a long lunch. FWIW they were *not* doing these framings 38 years ago. #DataPoint
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That's the 74193 (4-bit counter) and 7473 (j-K flip-flop) simulations added and the six-bit Memory Sync counter functioning.
The bottom rows of the screenshot: Z101 is the 74193, Z101-Pad12 is the carry out. Z115 is the 7473.
The screenshot slow slightly over one complete 'rotation' of the memories. This is required for random memory access (reading/writing data).
The Clocks data is actually half-cycles but halving that to >6000 shows how slow this machine is.
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That's the 74193 (4-bit counter) and 7473 (j-K flip-flop) simulations added and the six-bit Memory Sync counter functioning.
The bottom rows of the screenshot: Z101 is the 74193, Z101-Pad12 is the carry out. Z115 is the 7473.
The screenshot slow slightly over one complete 'rotation' of the memories. This is required for random memory access (reading/writing data).
The Clocks data is actually half-cycles but halving that to >6000 shows how slow this machine is.
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Added code to the simulator to count clock cycles and drive certain inputs as required to initialise the processor (see previous thread).
It's running as far as requiring the WORD_SELECT signal which will initiate the first instruction fetch.
At this point I need to add a few more components to the simulator for the program counter and address counter sync logic which generates WORD_SELECT.
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Added code to the simulator to count clock cycles and drive certain inputs as required to initialise the processor (see previous thread).
It's running as far as requiring the WORD_SELECT signal which will initiate the first instruction fetch.
At this point I need to add a few more components to the simulator for the program counter and address counter sync logic which generates WORD_SELECT.
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This feels like a good time to look at what is needed to start the #Datapoint 2200 processor.
The Datapoint has no ROM, not even a boot ROM. On reset it rewinds tape deck 1, loads the first file, and executes it. All of this is done in hardware.
🧵
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This feels like a good time to look at what is needed to start the #Datapoint 2200 processor.
The Datapoint has no ROM, not even a boot ROM. On reset it rewinds tape deck 1, loads the first file, and executes it. All of this is done in hardware.
🧵
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The #Datapoint 2200 gate simulator can now import data from multiple projects and I can join boards together via connectors. So I now have the Decoder, Motherboard and Processor boards imported with net data propagating across them.
Some of the nets can have multiple drivers across different boards, so the simulator needs to examine all pins across the joined nets, and propagate the results back to all pins.
I'm now adding tooling ready to try and boot the processor, such as the scaling here.
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The #Datapoint 2200 gate simulator can now import data from multiple projects and I can join boards together via connectors. So I now have the Decoder, Motherboard and Processor boards imported with net data propagating across them.
Some of the nets can have multiple drivers across different boards, so the simulator needs to examine all pins across the joined nets, and propagate the results back to all pins.
I'm now adding tooling ready to try and boot the processor, such as the scaling here.
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My #Datapoint 2200 net simulator is now generating output which matches my analysis of the Decoder board schematic (see comments on the image).
One full cycle takes 80 clocks. First SYS_CLK is divided in two and split into four T states. T0 clocks a decade counter (C0..C4). Most outputs are a combination of counter and T states.
Counts 0 to 7 are when memory and/or registers are clocked (PHIxx). Counts 8 and 9 are when 'other' stuff happens (STROBEx).
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The #Datapoint processor board is large, expensive, and will take a long time to solder up. It could have errors from my transcribing the schematics or the schematics themselves. It may even have deliberate traps to stop competitors stealing the design.
I really need a way to prove the design works. I could use Logisim for that. But re-entering the whole thing would take ages, and have issues of it's own (and assuming it could cope with the design).
1/n