#microarchitectures — Public Fediverse posts

It seems like someone at Intel has noticed that booting a 64-bit processor in 16-bit mode, then hitting it on the head to move it to 32-bit mode and then kicking it up the backside to move it to 64-bit mode was a bit excessive in 2023 (I guess we should be grateful that they no longer need the 8259 to move from "real" to "fantasy" mode).

Welcome "Simplified Intel Architecture"¹² which is trying to remove the cruft from amd64 (sorry, could not avoid the dig) which, if we want to be terribly pedantic, is going to be an issue to the following:

* BIOS manufacturers being dragged screaming and shouting into UEFI,
* people like me who use old and obscure extensions to mix potions of dubious consequences and appreciate the cruft in this game of shadows and mirrors,
* firmware manufacturers who rely on OROM processing by the BIOS to turn on their cards,
* arguably OS vendors who no longer have to dance the dance but "just boot" into 64-bit mode.

Of course the fun begins when (like Apple back in the MacPro days) you discover that tons of (U)EFI installs are 32-bit but that's a separate issue :flan_molotov:

I am somewhat miffed that Intel pushes this out after several years ago I sent them a proposal to, at least, be able to turn off extensions trivially and I am even more miffed that they are not considering my other proposal which is to actually open the µcode and make _that_ the new ISA.

Anyway, chances are that amd64 Mk.II will just be another emulated architecture on someone's better chip design (*cough* *cough* Rosetta 2…).

:cm_2:​

#Intel #X866 #amd64 #microarchitectures #processors
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¹ https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html
² https://cdrdv2.intel.com/v1/dl/getContent/776648

Ultimately it will not really matter what ISA you decide to programme to as emulators and transpilers will make it run anywhere¹.

#Processors #Microarchitectures
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¹ subject to terms and conditions such as: a decent underlying ISA.

D. Soni et al., "RPU: The Ring Processing Unit"¹

Ring-Learning-with-Errors (RLWE) has emerged as the foundation of many important techniques for improving security and privacy, including homomorphic encryption and post-quantum cryptography. While promising, these techniques have received limited use due to their extreme overheads of running on general-purpose machines. In this paper, we present a novel vector Instruction Set Architecture (ISA) and microarchitecture for accelerating the ring-based computations of RLWE. The ISA, named B512, is developed to meet the needs of ring processing workloads while balancing high-performance and general-purpose programming support. Having an ISA rather than fixed hardware facilitates continued software improvement post-fabrication and the ability to support the evolving workloads. We then propose the ring processing unit (RPU), a high-performance, modular implementation of B512. The RPU has native large word modular arithmetic support, capabilities for very wide parallel processing, and a large capacity high-bandwidth scratchpad to meet the needs of ring processing. We address the challenges of programming the RPU using a newly developed SPIRAL backend. A configurable simulator is built to characterize design tradeoffs and quantify performance. The best performing design was implemented in RTL and used to validate simulator performance. In addition to our characterization, we show that a RPU using 20.5mm2 of GF 12nm can provide a speedup of 1485x over a CPU running a 64k, 128-bit NTT, a core RLWE workload

#arXiv #ResearchPapers #RLWE #microarchitectures #ISA #HardwareAcceleration
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¹ https://arxiv.org/abs/2303.17118