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#mdspan — Public Fediverse posts

Live and recent posts from across the Fediverse tagged #mdspan, aggregated by home.social.

  1. Matthias Kretz | Vir @[email protected] ·

    I've been looking into matrix multiplication using std::simd and std::mdspan/submdspan (all single-threaded).
    I got to 86% of peak FLOP. x86_64 AVX2 has 32/16 FLOP/cycle peak (2 FMAs per cycle).
    I suspect better performance needs a more cache-friendly layout mapping. This is using layout_right.

    #stdsimd #simd #mdspan #cpp26 #cpp

    #stdsimd #simd #mdspan #cpp26 #cpp
  2. Matthias Kretz | Vir @[email protected] ·

    I've been looking into matrix multiplication using std::simd and std::mdspan/submdspan (all single-threaded).
    I got to 86% of peak FLOP. x86_64 AVX2 has 32/16 FLOP/cycle peak (2 FMAs per cycle).
    I suspect better performance needs a more cache-friendly layout mapping. This is using layout_right.

    #stdsimd #simd #mdspan #cpp26 #cpp

    #stdsimd #simd #mdspan #cpp26 #cpp
  3. Matthias Kretz | Vir @[email protected] ·

    I've been looking into matrix multiplication using std::simd and std::mdspan/submdspan (all single-threaded).
    I got to 86% of peak FLOP. x86_64 AVX2 has 32/16 FLOP/cycle peak (2 FMAs per cycle).
    I suspect better performance needs a more cache-friendly layout mapping. This is using layout_right.

    #stdsimd #simd #mdspan #cpp26 #cpp

    #stdsimd #simd #mdspan #cpp26 #cpp
  4. Matthias Kretz | Vir @[email protected] ·

    I've been looking into matrix multiplication using std::simd and std::mdspan/submdspan (all single-threaded).
    I got to 86% of peak FLOP. x86_64 AVX2 has 32/16 FLOP/cycle peak (2 FMAs per cycle).
    I suspect better performance needs a more cache-friendly layout mapping. This is using layout_right.

    #stdsimd #simd #mdspan #cpp26 #cpp

    #cpp #cpp26 #mdspan #simd #stdsimd
  5. Matthias Kretz | Vir @[email protected] ·

    I've been looking into matrix multiplication using std::simd and std::mdspan/submdspan (all single-threaded).
    I got to 86% of peak FLOP. x86_64 AVX2 has 32/16 FLOP/cycle peak (2 FMAs per cycle).
    I suspect better performance needs a more cache-friendly layout mapping. This is using layout_right.

    #stdsimd #simd #mdspan #cpp26 #cpp

    #stdsimd #simd #mdspan #cpp26 #cpp