#cortexm7 — Public Fediverse posts

This is surprising: It looks like the Cortex-M7 may be able to execute a three-argument addition in a single cycle, at least under narrow circumstances.

Specifically, it appears that a two-instruction sequence of the form

ADD.W R1, R0, R3
ADD.W R1, R1, R2

...can successfully pair and dual-issue, performing the equivalent of

R1 = R0 + R2 + R3

in one cycle. This isn't impossible; the register file has four read ports to support the fancy MAC instructions.

(Other forms of adds might also qualify, my script is just restricted to testing 32-bit instruction encodings for the time being, for simplicity.)

#cortexm7

This is surprising: It looks like the Cortex-M7 may be able to execute a three-argument addition in a single cycle, at least under narrow circumstances.

Specifically, it appears that a two-instruction sequence of the form

ADD.W R1, R0, R3
ADD.W R1, R1, R2

...can successfully pair and dual-issue, performing the equivalent of

R1 = R0 + R2 + R3

in one cycle. This isn't impossible; the register file has four read ports to support the fancy MAC instructions.

(Other forms of adds might also qualify, my script is just restricted to testing 32-bit instruction encodings for the time being, for simplicity.)

#cortexm7

Some more random observations on dual-issue restrictions on Cortex-M7:

- Only one "shifted operand" instruction can be issued per cycle (e.g. ADD R0, R1, R2, LSL #4)
- Bitfield manipulation operations count as having shifted operands
- Sign and zero extension operations _also_ count as having shifted operands
- Immediates that don't fit entirely in the bottom 8 bits do too (e.g. AND R0, #0x7e0)
- DSP/SIMD operations can only participate in dual-issue from the _lower address_ of a pair of instructions, even if there's no data dependency -- this includes the things you'd expect but also REV for swapping bytes in a word!
- The input for a shifted operand has to be available one cycle earlier than other inputs or you take a stall (this includes bitfield operations)
- Recall that this is an in-order processor despite being dual-issue, so if the instruction at the lower address can't issue due to a stall, neither issues.

Some of these observations appear to be novel and contradict some other reverse engineers, but I'm very confident in my tests.

#cortexm7 #reverseengineering

Some more random observations on dual-issue restrictions on Cortex-M7:

- Only one "shifted operand" instruction can be issued per cycle (e.g. ADD R0, R1, R2, LSL #4)
- Bitfield manipulation operations count as having shifted operands
- Sign and zero extension operations _also_ count as having shifted operands
- Immediates that don't fit entirely in the bottom 8 bits do too (e.g. AND R0, #0x7e0)
- DSP/SIMD operations can only participate in dual-issue from the _lower address_ of a pair of instructions, even if there's no data dependency -- this includes the things you'd expect but also REV for swapping bytes in a word!
- The input for a shifted operand has to be available one cycle earlier than other inputs or you take a stall (this includes bitfield operations)
- Recall that this is an in-order processor despite being dual-issue, so if the instruction at the lower address can't issue due to a stall, neither issues.

Some of these observations appear to be novel and contradict some other reverse engineers, but I'm very confident in my tests.

#cortexm7 #reverseengineering

Neural Guitar Pedal – Optimizing NAM for Daisy Seed Arm Cortex-M7

https://www.tone3000.com/blog/running-nam-on-embedded-hardware

#HackerNews #NeuralGuitarPedal #NAM #Optimization #DaisySeed #CortexM7 #EmbeddedHardware

Neural Guitar Pedal – Optimizing NAM for Daisy Seed Arm Cortex-M7

https://www.tone3000.com/blog/running-nam-on-embedded-hardware

#HackerNews #NeuralGuitarPedal #NAM #Optimization #DaisySeed #CortexM7 #EmbeddedHardware

Compact SMARC module combines Linux, AI, and vision on i.MX 8M Plus

https://fed.brid.gy/r/https://linuxgizmos.com/compact-smarc-module-combines-linux-ai-and-vision-on-i-mx-8m-plus/

On i.MX8MP, GPIOs are owned by Linux (A53) by default.
If the Cortex-M7 needs them—especially for interrupts—you must release them in the device tree:

• Remove pinmux
• Remove GPIO references
• Disable the GPIO controller if needed

This prevents A53/M7 resource conflicts and ensures real-time reliability.
https://www.forlinx.net/industrial-news/imx8mp-m7-gpio-release-linux-pinmux-769.html

#iMX8MP #CortexM7 #EmbeddedLinux #GPIO #RTOS

New Teensy 4.0 Blows Away Benchmarks, Implements Self-Recovery, Returns to Smaller Form - Paul Stoffregen did it again: the Teensy 4.0 has been released. The latest in the Teensy microcontro... more: https://hackaday.com/2019/08/07/new-teensy-4-0-blows-away-benchmarks-implements-self-recovery-returns-to-smaller-form/ #microcontrollers #developmentboard #teensyduino #teensy4.0 #featured #cortexm7 #reviews #arduino #news