Search
263 results for “bread80”
-
And the current routing status. Nine pages of schematics done. Three left to go.
-
And the current routing status. Nine pages of schematics done. Three left to go.
-
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.
-
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.
-
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.
-
It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.
-
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
-
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
-
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
-
Onto the A register. This uses a pair of 7495 4-bit parallel in, parallel out, shift registers. The top of the schematic is the input bus, the bottom is the two(!) output busses.
While the processor is 1-bit serial it can communicate with other devices over these parallel busses. I'm not sure why there are two output busses though.
On the PCB you're looking at the six chips on the right for the register and input and output buffers/inverters.
-
And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.
The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.
-
And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.
The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.
-
And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.
The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.
-
And the address multiplexers. Data can be loaded into the address registers from 3 sources: the stack, the H and L registers or the temp address register. The multiplexers select the source.
The Temp Address Register is used when reading a call or jump inline address. These are the only instructions which take an immediate address. All other memory references have to go via the H and L registers.
-
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
-
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
-
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
-
Another page of schematics done - the stack. An A4 page with few external connections and quite quick to route. :phew:
Z95 to 99 are the stack, Z100 the stack up/down counter. Z109 to Z112 are the address register/counters. Z101, 114 and 115 clock the memory until they match the address on A0 to A6. A7 to A10 are sent to the memory cards (top-right) for decoding on the board. Z79 decodes A11 and A12 to select a memory card.
-
All components placed - to match the positions on the original board. Still some fettling to do on the edge connectors.
I'm now finally realising how ridiculously large this board is. In a way which, for unknown reasons, I'd been completely oblivious to previously.
-
All components placed - to match the positions on the original board. Still some fettling to do on the edge connectors.
I'm now finally realising how ridiculously large this board is. In a way which, for unknown reasons, I'd been completely oblivious to previously.
-
All components placed - to match the positions on the original board. Still some fettling to do on the edge connectors.
I'm now finally realising how ridiculously large this board is. In a way which, for unknown reasons, I'd been completely oblivious to previously.
-
All components placed - to match the positions on the original board. Still some fettling to do on the edge connectors.
I'm now finally realising how ridiculously large this board is. In a way which, for unknown reasons, I'd been completely oblivious to previously.
-
The Puppy can now handle both 16 and 8 bit values. I ended up making everything 8-bit. 16 bit operations simply need to work on both halves of their data.
So moving DE to HL know generates solutions using EX HL,DE as well as two LDs. The solution with an extra load is valid since it causes different collateral. The real question is why it doesn't generate the HL L,E alternative.