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263 results for “bread80”
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The #Datapoint processor board is large, expensive, and will take a long time to solder up. It could have errors from my transcribing the schematics or the schematics themselves. It may even have deliberate traps to stop competitors stealing the design.
I really need a way to prove the design works. I could use Logisim for that. But re-entering the whole thing would take ages, and have issues of it's own (and assuming it could cope with the design).
1/n
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I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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I'm adding a basic terminal to the #Datapoint 2200 simulator. It's listening to output ports (input still to do).
Here's a video of it saying "Hello World" in it's own fashion. Program listing in video comments.
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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"A programmer that's never programmed a computer in binary is like a child that's never run barefoot over Lego."
Also can you spot the schoolboy error in the first line of code? Which means all the jump target addresses are wrong and I need to redo a lot of stuff.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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I fixed the ALU issue. The clock input of the carry flag latch wasn't triggering. The circuit uses a couple of open-collector gates and a pull-up. A bug in my simulator failed to recognise the net's rising edge.
A few upgrades to the simulator so it can free run and some speed ups. Below is after adding 1 to A and looping until the carry flag is set, using a JFC (Jump if Carry False) and HALTing.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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Todays test program: load values into the A and B registers, add (or subtract) them and loop.
I've got the jump working but the ALU ops are not so pretty. It's inverting each bit of A if the bit in B is set. The circuit for the ALU is all standard gates, and I'd be surprised if there's any bugs in there given the rest of the simulator is working so well.
So it's probably a schematic issue, and one which will take a bit of debugging.
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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"Hello!!" (Read the registers from top to bottom <g>).
(I had to fix a bug in the 7474 simulation to get this to run. It was listening to the SET and RSET pins if they went low. But the design had both low at the same time, the first one to go high 'lost'. The simulator now updates if either pin changes to any state (it already checks them to overrides CLK updates they're active)).
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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I've spent much of the weekend working on my gate level logic simulator of the #Datapoint 2200 serial processor.
Here it is after processing a LA 6 instruction, which loads the immediate value 6 into the A register (6 is also the bytecode for LA n).
So far the schematics have functioned flawlessy, the only bugs have been in the simulator code.
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And the current routing status. Nine pages of schematics done. Three left to go.
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And the current routing status. Nine pages of schematics done. Three left to go.
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And the current routing status. Nine pages of schematics done. Three left to go.
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And the current routing status. Nine pages of schematics done. Three left to go.
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It's worth noting that this circuit functions for every opcode in the instruction register even if it's not a branch instruction.
It's only at the next stage that the processor examines whether the opcode is a jump, call or return and sends signals elsewhere to load an immediate address, push the program counter on the stack or pop a return address off the stack.