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  1. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  2. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  3. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  4. Well, I've not found a suitable UART speed for comms between the 20MHz AVR for keyboard and modem and the CPLD, it's 55336 baud, the AVR has a 0.4% error which gives 55556 baud, which *should* be ok with the CPLD running on a divided down 28.332MHz.
    So it spits out 1 ASCII character a second to the CPLD.
    Later this week I'll get the UART code into the CPLD and write a bit of basic to read it, hopefully it works.
    #Retrocomputing #LT6502b #ILaughAtStandards

  5. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  6. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  7. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  8. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  9. Ok, so, I have the next part working of my CPLD UART... it now populates a buffer, with the correct values!!
    Green = serial in (LSB first),
    Orange is parallel out (LSB at the bottom)

    Next step is to transfer that to a register that can be read!

    I will probably up my sample clock to 16x, as that seems like the common thing, and 4x may not be 100% reliable. But for simulation, 4x is enough.

    #CPLD #LT6502b

  10. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  11. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  12. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  13. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  14. Fun with WinSim.

    After much battling with dodgy tools from the 90s, I've now got two useful signals. One to start the UART receive and it's counter, and one to stop when the 10th bit is received.

    Tomorrow, shift register to capture the bits.

    #Retrocomputing #LT6502b #CPLD

  15. I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
    I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

    So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

    Has anyone done a UART in a CPLD?

    #LT6502b

  16. I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
    I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

    So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

    Has anyone done a UART in a CPLD?

    #LT6502b

  17. I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
    I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

    So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

    Has anyone done a UART in a CPLD?

    #LT6502b

  18. I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
    I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

    So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

    Has anyone done a UART in a CPLD?

    #LT6502b

  19. I've been trying to get my KeyScan (ATMEGA644P) to output onto the 65c02 databus at the correct time and for the correct duration...
    I don't think it's going to work, sometimes I get no data back, when I tweak the timing I somehow get a 16bit value back (impressive from an 8 bit CPU eh?).

    So, I may have to put a UART into the CPLD, and "WinSim" doesn't seem to simulate properly. So it'll be try and keep trying until it works, or I run out of space.

    Has anyone done a UART in a CPLD?

    #LT6502b

  20. Well it completed.
    No lines so I think the fix has solved the timing issue.
    32 iterations, 1024x600 Mandelbrot on #LT6502b

  21. Well it completed.
    No lines so I think the fix has solved the timing issue.
    32 iterations, 1024x600 Mandelbrot on #LT6502b

  22. Well it completed.
    No lines so I think the fix has solved the timing issue.
    32 iterations, 1024x600 Mandelbrot on #LT6502b

  23. Well it completed.
    No lines so I think the fix has solved the timing issue.
    32 iterations, 1024x600 Mandelbrot on #LT6502b

  24. Well it completed.
    No lines so I think the fix has solved the timing issue.
    32 iterations, 1024x600 Mandelbrot on #LT6502b

  25. Looks like it’s to bin my iPhone. No Mr Cook I will NOT give you a scan of my driving license.
    I’m looking at a fairphone with e/OS, anyone have any experience with these?
    #NoAgeVerification